JAJSHM6E june   2019  – february 2021 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
    1.     Pin Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  10.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 LLC Rectifier Diodes
        13. 8.2.2.13 LLC Output Capacitors
        14. 8.2.2.14 HV Pin Series Resistors
        15. 8.2.2.15 BLK Pin Voltage Divider
        16. 8.2.2.16 ISNS Pin Differentiator
        17. 8.2.2.17 VCR Pin Capacitor Divider
        18. 8.2.2.18 BW Pin Voltage Divider
        19. 8.2.2.19 Soft Start and Burst Mode Programming
      3. 8.2.3 Application Curves
  11. 8 Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

7.4.3 Burst Mode Control

The efficiency of an LLC converter power stage drops rapidly with falling output power. To maintain reasonable light load efficiency it is necessary to operate the LLC converter in burst mode. In this mode the LLC converter operates at relatively high power for a short burst period and then switching is stopped for a time period. During the burst period excess charge is transferred to and stored in the output capacitor. During the burst off period this stored charge is used to supply the load current. The burst mode operation is critical to meet strict standby power consumption requirements. But a challenge with burst mode operation is the audible noise performance. Due to the need to stop switching for certain time, there will be a pattern of switching pulses with frequencies that fall within the audible frequency range from 20 Hz to 20 kHz. Some device variants of UCC25640x includes a burst mode with soft on and soft off periods at the first few and last few switching pulses, minimizing the audible noise during standby operation.

Figure 7-17 describes the timing diagram of the burst mode operation. Two burst mode thresholds are used (BMTH for burst mode exit and BMTL for burst mode entry). The details of how to program these two thresholds are described in Section 7.4.3.1 section. The FBreplica from the FB chain is compared with the two thresholds, and determines the burst mode operation.

  • At t1, FBreplica is below BMTL. The system enters burst mode and stops switching immediately. During the burst off period, UCC25640x disables some internal blocks to save power consumption.
  • At t2, FBreplica is above BMTH. The system starts to switch again, and this period is referred to as the burst on period. During burst on period, the control effort Vcomp sent to the VCR comparator is the higher value of FBreplica and BMTL. For the first switching pattern after the system enters burst mode, there is no burst soft on.
  • At t3, FBreplica falls below BMTL again. Switching will not stop until it reaches the predefined number (Nburst) of a burst packet. The Vcomp still selects the higher value of FBreplica and BMTL. For the last 7 switching cycles, soft off will be applied (only 3 soft on/off steps are shown in Figure 7-17 for conceptual introduction). The Vcomp is a fraction of the higher value between FBreplica and BMTL. The number of fractions for different switching cycles are described in Table 7-1. For burst soft off, it starts from step 7 and ramps down. After it reaches step 1, soft off steps are completed and the system enters burst off period. This helps to achieve slow ramping down of the LLC transformer current. For burst soft on, it reverses the direction by starting from step 1 and ends at step 7. If FBreplica becomes greater than BMTL before the soft off steps are completed, the burst soft off will end immediately and the system transitions to burst soft on. In this condition, the soft on step starts from the step where soft off ends at, to ensure a smooth transition between soft off and soft on.
  • At t4, FBreplica is greater than BMTL. The system enters burst on period, and since this is not the first burst on period, there is soft on period at the first 7 switching cycles. The fraction of Vcomp to the higher value of FBreplica and BMTL is also described in Table 7-1. After burst soft on steps are completed, Vcomp uses the higher value of FBreplia and BMTL until it reaches burst soft off periods.
  • At t5, FBreplica is greater than BMTL again after another burst off period. This time the difference is that FBreplica is greater than BMTH at t6, when the burst soft on steps are not completed yet. The burst soft on will get terminated immediately, so that Vcomp can follow the FBreplica. This is to ensure a quick system response during a load transient from burst mode operation to out-of-burst mode operation.
GUID-ECC9030F-D444-42FB-B8DE-784B1A22CC9F-low.gifFigure 7-17 Burst Mode Switching Pattern
Table 7-1 Burst Mode Soft On and Soft Off Vcomp Control
Burst Soft On and Soft Off StepFraction used for Reduced Vcomp During Soft On
11/3
29/21
311/21
413/21
515/21
617/21
719/21

The HHC control makes the implementation of the burst soft on and soft off very straight forward. Due to the frequency control portion in HHC, changing the Vcomp can directly impact the LLC switching frequency to control the resonant current magnitude within switching cycles. Also the last pulse of each burst on period is turned off when the VCR node voltage equals the common mode voltage VCM. In HHC control, this is approximately equivalent to resonant capacitor voltage equal to VIN/2. This operation keeps the resonant capacitor voltage to approximate VIN/2 for each burst off period, thus enabling the burst pattern to settle as soon as possible during the burst on period.

As described in Section 7.3.9.1, in order to avoid nuisance ZCS detection at light load condition, ZCS is disabled at light load condition. This is achieved by using the BMTH threshold. When FBreplica is below BMTH, indicating a light load operating condition, ZCS detection is disabled. When FBreplica is above BMTH, ZCS detection will resume.

Some device variants disables the burst soft on and soft off feature, for applications that have less concern about audible noise, but want smaller output ripple during burst mode. A smaller burst packet size is also used. The timing diagram of the burst mode operation for when burst soft on and soft off is disabled is described in Figure 7-18.

  • At t1, FBreplica is below BMTL. The system enters burst mode and stops switching immediately.
  • At t2, FBreplica is above BMTH. The system starts to switch again, and enters burst on period. The control effort Vcomp sent to the VCR comparator is the higher value of FBreplica and BMTL.
  • At t3, FBreplica falls below BMTL again. Switching will not stop until it reaches the predefined number (Nburst) of a burst packet. If switching reaches the Nburst before FBreplica falls below BMTL again, system will continue to deliver burst packet until FBreplica is below BMTL.
  • At t4, FBreplica is greater than BMTL. The system enters burst on period without soft on. So the control effort Vcomp is the higher value of FBreplica and BMTL.
  • At t5, FBreplica is greater than BMTL again after another burst off period. The control effort Vcomp follows FBreplica. At t6, FBreplica becomes above BMTH, Vcomp still follows FBreplica. If FBreplica remains above BMTH more than Nburst switching cycles, system exits burst mode.
GUID-79942718-B976-4018-9091-A46300DF2FD1-low.gifFigure 7-18 Burst Mode Switching Pattern when Soft On and Soft Off is Disabled

UCC25640x can also disable the burst mode by changing the BW pin resistance, as described in Section 7.4.3.2. When burst mode is disabled, the switching does not stop even when FBreplica becomes lower than BMTL. The pick higher block still works by picking the higher value of BMTL and FBreplica for the control effort Vcomp. In this case, BMTL will limit the maximum switching frequency of LLC.

When burst mode is disabled, FBreplica needs to be higher than BMTL at steady state. Otherwise, LLC output voltage will lose regulation as it continues deliver more energy than what is demanded from the feedback. For a transient period, it is ok for FBreplica to be lower than BMTL.