JAJSLX3K September   2011  – August 2022 BQ294502 , BQ294504 , BQ294506 , BQ294512 , BQ294522 , BQ294524 , BQ294532 , BQ294533 , BQ294534 , BQ294582 , BQ294592

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sense Positive Input for VX
      2. 8.3.2 Output Drive, OUT
      3. 8.3.3 Supply Input, VDD
      4. 8.3.4 Thermal Pad, PWRPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 OVERVOLTAGE Mode
      3. 8.4.3 Customer Test Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

Figure 6-1 DRV Package6-Pin SONTop View
Table 6-1 Pin Functions
NUMBER NAME TYPE(1) DESCRIPTION
1 V3 IA Sense input for positive voltage of the third cell from the bottom of the stack.
2 V2 IA Sense input for positive voltage of the second cell from the bottom of the stack.
3 VSS P Electrically connected to IC ground and negative terminal of the lowest cell in the stack.
4 V1 IA Sense input for positive voltage of the lowest cell in the stack.
5 VDD P Power supply
6 OUT OA1 Output drive for external N-channel FET.
— PWRPAD — VSS pin to be connected to the PWRPAD on the printed-circuit-board (PCB) for proper operation.
(1) IA = Input Analog, OA = Output Analog, P = Power Connection