JAJSM24A December   2023  – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics - DC Specifications

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY (25 MSPS)
No missing codes No missing codes 10 bits
DNL Differential nonlinearity -0.95 ±0.4 2.1 LSB
INL Integral nonlinearity -2 ±0.5 2.1 LSB
VOS_ERR Offset error -2.75 ±1 2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error External Reference -2.25 ±0.2 2.25 %FSR
Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature External Reference -35 ppm/ºC
Internal Reference -102 ppm/ºC
DC ACCURACY (65 MSPS)
No missing codes No missing codes 10 bits
DNL Differential nonlinearity -0.95 ±0.4 2.1 LSB
INL Integral nonlinearity -2 ±0.5 2.1 LSB
VOS_ERR Offset error -2.75 ±1 2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error External Reference -2.25 ±0.2 2.25 %FSR
Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature External Reference -35 ppm/ºC
Internal Reference -102 ppm/ºC
DC ACCURACY (125 MSPS)
No missing codes No missing codes 10 bits
DNL Differential nonlinearity -0.95 ±0.4 2.1 LSB
INL Integral nonlinearity -2 ±0.5 2.1 LSB
VOS_ERR Offset error -2.75 ±1 2.75 LSB
VOS_DRIFT Offset drift over temperature 0.001 LSB/ºC
GAINERR Gain error External Reference -2.25 ±0.3 2.25 %FSR
Internal Reference ±0.8 %FSR
GAINDRIFT Gain drift over temperature External Reference -35 ppm/ºC
Internal Reference -102 ppm/ºC
ADC ANALOG INPUT (INAP/M, INBP/M)
FS Input full scale Differential  1.9 Vpp
Single-ended 0.95 Vpp
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VCM Input common mode voltage VOCM - 50mV 1.275 VOCM + 50mV V
VOCM Output common mode voltage 1.25 V
BW Analog Input Bandwidth (-3dB) 150 MHz
EXTERNAL VOLTAGE REFERENCE (VREF)
VREF External voltage reference 1.2 V
Input Current 0.1 mA
Input impedance 12 kΩ
CLOCK INPUT 
Input clock frequency 5 125 MHz
VIH High level input voltage AVDD - 0.3 1.8 V
VIL Low level input voltage 0 AVSS + 0.3 V
CIN Input capacitance 0.5 pF
Clock duty cycle 45 50 55 %
DIGITAL INPUTS (DCLKIN, RESET, OEN, SCLK, SEN, SDIO)
VIH High level input voltage DCLKIN AVDD - 0.1 AVDD V
VIL Low level input voltage 0.1 V
VIH High level input voltage RESET, OEN, SCLK, SEN, SDIO 1.4 V
VIL Low level input voltage 0.4 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL OUTPUT (SDOUT)
VOH High level output voltage ILOAD = -400 uA AVDD - 0.1 AVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
DIGITAL CMOS OUTPUTS (D0:D11)
Output data rate per CMOS output pin 250 MHz
VOH High level output voltage ILOAD = -400 uA IOVDD - 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
VOH High level output voltage ILOAD = -400 uA, ALERT/GPO IOVDD - 0.1 IOVDD V
VOL Low level output voltage 0.1 V