JAJSMH7D April   2020  – May 2024 UCC27624

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
      5. 6.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.1 Operating Supply Current

The UCC27624 device features low quiescent IDD currents. The typical operating supply current in UVLO state and fully-on state (under static and switching conditions) are summarized in the Electrical Characteristics table. The lowest quiescent current (IDD) is achieved when the device is fully on and the outputs are in a static state (DC high or DC low). During this state, all of the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current because of switching, and any current related to pullup resistors on the enable pins. Knowing the operating switching frequency (fSW) and the MOSFET gate charge (QG) at the drive voltage being used, the average IOUT current can be calculated as product of QG and fSW.

Typical Characteristics provides a complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages. The linear variation and close correlation with the theoretical value of the average IOUT indicate a negligible shoot-through inside the gate driver device, displaying its high-speed characteristics.