JAJSSU3A January 2024 – July 2024 LMG3100R017 , LMG3100R044
PRODUCTION DATA
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
NC | 1, 5, 11–13, 15 | — | Not connected internally. Leave floating. |
LI | 2 | I | Low-side gate driver control input. |
VCC | 3 | P | 5V device power supply. |
AGND | 4 | G | Analog ground. |
SRC | 6 | P | Source of GaN FET. Internally connected to AGND. |
DRN | 7 | P | Drain of GaN FET. |
HS | 8 | P | Bootstrap voltage ground reference. |
HB | 9 | P | High-side gate driver bootstrap rail with HS as the ground reference. |
HO | 10 | O | Level shifted high-side gate driver control output. |
HI | 14 | I | High-side gate driver control input. |