SBAA583 july   2023 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1 , PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 AC Coupled Systems
    2. 1.2 DC Coupled System
  5. 2AC Coupling Schemes
    1. 2.1 Equivalent Circuit
    2. 2.2 Input Pin Waveforms with AC Coupling
    3. 2.3 Selection of Coupling Capacitor
    4. 2.4 Quick Charge Circuit
    5. 2.5 Selection of Capacitor Type
    6. 2.6 Single-Ended and Differential Mode
    7. 2.7 S.N.R in AC Coupled Circuits
  6. 3DC Coupled Scheme
    1. 3.1 Biasing the Pins
    2. 3.2 Electrical Characteristics
    3. 3.3 Application Circuits
      1. 3.3.1 S.N.R in DC Coupled Circuits
  7. 4Application Examples
    1. 4.1  Electret Condenser Microphone: Single Ended DC- Coupled Input
    2. 4.2  Electret Condenser Microphone: Single Ended AC Coupled Input
    3. 4.3  Selection of a Microphone
    4. 4.4  Condenser Microphone: Differential DC-Coupled Input
    5. 4.5  Condenser Microphone: Differential AC-Coupled Input
    6. 4.6  MEMS Microphone: Differential AC Coupled Input
    7. 4.7  Circuit With No Offset and Response Down to DC
    8. 4.8  Improving SNR by Summing the Output of 2 ADC Channels
    9. 4.9  Measure a High Voltage Waveform (+-50 V)
    10. 4.10 I2C Listing
  8. 5Summary
  9. 6References

4.7 Circuit With No Offset and Response Down to DC

As shown in Figure 4-13 and Figure 4-14, the all-pass filter of the ADC is switched on to achieve a frequency response down to DC. Turning on the all-pass filter results in a DC offset at the output, which is controlled by the DSP_CFGO register.

Table 4-1 DSP_CFG0 Register Field Descriptions
Bit Field Type Reset Description
7-6 Reserved R 0h Reserved
5-4 DECI_FILT[1:0] R/W 0h Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3d = Reserved
3-2 CH_SUM[1:0] R/W 0h Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2 and a (CH3 + CH4) / 2 output
2d = 4-channel summation mode is enabled to generate a (CH1 + CH2 + CH3 + CH4) / 4 output
3d = Reserved
1-0 HPF_SEL[1:0] R/W 1h High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 × fS (12 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.002 × fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 × fS (384 Hz at fS = 48 kHz) is selected

To remove the DC offset, the INxM pin DC voltage is equal to the average level on the VIN pin resulting in the DC offset removed at ADC output.

GUID-20230501-SS0I-RKTK-RM8F-C4DMG031HTHN-low.svgFigure 4-13 Waveform
GUID-20230512-SS0I-CMM3-M7QF-4WRVQ6LFD07G-low.svgFigure 4-14 Circuit