SBAA583 july   2023 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1 , PCM3120-Q1 , PCM5120-Q1 , PCM6120-Q1 , TLV320ADC3120 , TLV320ADC5120 , TLV320ADC6120

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 AC Coupled Systems
    2. 1.2 DC Coupled System
  5. 2AC Coupling Schemes
    1. 2.1 Equivalent Circuit
    2. 2.2 Input Pin Waveforms with AC Coupling
    3. 2.3 Selection of Coupling Capacitor
    4. 2.4 Quick Charge Circuit
    5. 2.5 Selection of Capacitor Type
    6. 2.6 Single-Ended and Differential Mode
    7. 2.7 S.N.R in AC Coupled Circuits
  6. 3DC Coupled Scheme
    1. 3.1 Biasing the Pins
    2. 3.2 Electrical Characteristics
    3. 3.3 Application Circuits
      1. 3.3.1 S.N.R in DC Coupled Circuits
  7. 4Application Examples
    1. 4.1  Electret Condenser Microphone: Single Ended DC- Coupled Input
    2. 4.2  Electret Condenser Microphone: Single Ended AC Coupled Input
    3. 4.3  Selection of a Microphone
    4. 4.4  Condenser Microphone: Differential DC-Coupled Input
    5. 4.5  Condenser Microphone: Differential AC-Coupled Input
    6. 4.6  MEMS Microphone: Differential AC Coupled Input
    7. 4.7  Circuit With No Offset and Response Down to DC
    8. 4.8  Improving SNR by Summing the Output of 2 ADC Channels
    9. 4.9  Measure a High Voltage Waveform (+-50 V)
    10. 4.10 I2C Listing
  8. 5Summary
  9. 6References

2.7 S.N.R in AC Coupled Circuits

The TLV320ADCX120 can also support a higher input common-mode tolerance at the expense of noise performance by a few decibels. The device supports three different modes with different common-mode tolerances, which can be configured using the CH1_INP_CM_TOL_CFG[1:0] (P0_R58_D[7:6]) register bits. Mode 0 gives the lowest noise performance.

Table 2-9 Common-Mode Tolerance Mode Selection for Record Channel
P0_R58_D[7:6] : CH1_INP_CM_TOL_CFG[1:0] Channel 1 Input Common-Mode Tolerance
00 (default) Channel 1 input common-mode tolerance: AC-coupled input = 100 mVPP, DC-coupled input = 2.82 VPP.
01 Channel 1 input common-mode tolerance: AC/DC-coupled input = 1 VPP.
10 (high CMRR mode) Channel 1 input common-mode tolerance: AC/DC-coupled input = 0-AVDD (supported only with an input impedance of 10 kΩ and 20 kΩ). For input impedance of 2.5 kΩ, the input common-mode tolerance is 0.4 V to 2.6 V.
11 Reserved, do not use this setting.

The highest performance for the ADC is obtained in AC coupling mode. To achieve the highest performance, the following setup must be implemented.

  • AC coupled mode
  • Differential operation
  • Mode 0 in page 0, register 58
  • Zin = 2.5 k
  • DRE Enabled
  • PGA Gain -0 db

For the TLV320ADC6120 device, the performance in Table 2-10 is achieved with the prior settings.

Table 2-10 SNR Data
SNR (DRE ON) dB SNR (DRE OFF) dB
Single-Ended 118 111
Differential 122 112