2 Target Mode Power Consumption with PLL Disabled

This section describes the typical current consumption of the TAA52xx devices, when the PLL is disabled, with AVDD set to 1.8V and 3.3V.

The PLL is disabled by setting the corresponding bit field B0_P0_R52[7] (PLL_DIS) and enabling (ADC_LOW_PWR_FILT) bit field: B0_P0_R78[2] with PLL disabled.

By default, the bit clock is used as the clock source to the internal block. Alternatively, an external clock source (CCLK) can be used in the device through one of the GPI-capable pins (GPIOx or GPIx), if the system has a low jitter clock available.

• If GPIOx is used for CCLK input, the appropriate GPIOx_CFG bit field in the GPIOx_CFG0 register must be configured for GPI function.
• If GPIx is used for CCLK input, the appropriate GPIx_CFG bit field in the GPI_CFG register must be enabled for GPI function.
• The pin configured for GPI must be configured as CCLK, this is done by configuring B0_P0_R15[6:5] (CCLK_SEL), based on the pin configured.
• With the CCLK configured, the external CCLK must be used as the clock source, this is done by configuring B0_P0_R52[3:1] (CLK_SRC_SEL).
• The CCLK must be synchronized with the frame sync. For example, the CCLK frequency must be an integer multiple of the frame sync frequency.
• Once configured, the device runs on the external CCLK as the clock source.

In Table 2-1, the power consumption measurements have all the biquad filters disabled, the ADC input (or inputs) is (are) grounded, and an external CCLK is provided as the clock source to the device through the GPIO1 pin.