SBAU412A November   2022  – May 2024 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7921 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Prerequisites
  6. 3 Typical Bare-Metal Design Flow
  7. 4 Background
  8. 5 Add Microblaze and SPI IP for Use in Vitis for Embedded Development
  9. 6 Create New Platforms in Vitis
  10. 7 Create New Application Projects in Vitis
  11. 8 Build Application Projects
  12. 9 Generate SPI Log for AFE79xx EVM
    1. 9.1 Generating the LMK SPI Log
    2. 9.2 Generating the AFE SPI Log
    3. 9.3 Converting SPI Logs to Format for Vitis
  13. 10AFE79xxEVM Board Modifications
  14. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  15. 12Configure the AXI SPI
  16. 13Set Up and Power on Hardware
  17. 14Set up ZCU102 Board Interface for VADJ_FMC
  18. 15Debug Application Projects and Set up Vitis Serial Terminal
  19. 16Execute the Application
  20. 17Revision History

14 Set up ZCU102 Board Interface for VADJ_FMC

To set the ZCU102 board interface for VADJ_FMC, follow these steps:

  1. Execute the ZCU102-Board User Interface software (available for download from Xilinx.com).
  2. Select the appropriate COM Port to enable communication between the onboard MSP430 of the ZCU102 and the PC. This software is required to turn on the FMC_AUX supply of 1.8V for the FMC bank of FPGA (see Figure 14-1).
    AFE7920 ZCU102 Board User Interface Figure 14-1 ZCU102 Board User Interface
  3. Select the Set VADJ to 1.8V check box (see Figure 14-2).
    AFE7920 Setting VADJ Figure 14-2 Setting VADJ
  4. Confirm the same by reading the VADJ_FMC voltage. The voltage value must be 1.80V (see Figure 14-3).
    AFE7920 VADJ_FMC Voltage Figure 14-3 VADJ_FMC Voltage