SBAU412A November   2022  – May 2024 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7921 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Prerequisites
  6. 3 Typical Bare-Metal Design Flow
  7. 4 Background
  8. 5 Add Microblaze and SPI IP for Use in Vitis for Embedded Development
  9. 6 Create New Platforms in Vitis
  10. 7 Create New Application Projects in Vitis
  11. 8 Build Application Projects
  12. 9 Generate SPI Log for AFE79xx EVM
    1. 9.1 Generating the LMK SPI Log
    2. 9.2 Generating the AFE SPI Log
    3. 9.3 Converting SPI Logs to Format for Vitis
  13. 10AFE79xxEVM Board Modifications
  14. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  15. 12Configure the AXI SPI
  16. 13Set Up and Power on Hardware
  17. 14Set up ZCU102 Board Interface for VADJ_FMC
  18. 15Debug Application Projects and Set up Vitis Serial Terminal
  19. 16Execute the Application
  20. 17Revision History

11.3 Setting High or Low for Corresponding Bits

XGpio_DiscreteWrite(&GPOs, 1, regval);

First argument &GPOs point to the GPIO instance initialized in previous command.

Second argument 1 indicates the GPIO bank. In this example, only the first bank is used.

Table 11-1 Bit Mapping of IP I/Os
Bit Description Bit Position
JESD RSTn 4
JESD TXRST 3
RSTn 2
RXTDD 1
TXTDD 0

For Example:

XGpio_DiscreteWrite(&GPOs, 1, 0x14);

This command sets JESD RSTn and RSTn to 1, sets all other bits to 0