The SMAART wire bus interface communicates over a single wire using a half-duplex UART (Universal Asynchronous Receiver Transmitter) interface. The half-duplex communication requires careful timing and mechanisms that prevent collisions on the bus. The auto-baud detection feature ensures that the temperature sensor always replies at the same communication speed (baud rate).

Figure 1-1 shows a snippet of the communication for the Address initialize command. The temperature sensor listens to the bus by default. Its input pin I/O is high impedance. The master device always initiates the communication first. The temperature sensor uses the first calibration byte 0x55 for baud rate detection. The second byte 0x95 corresponds to the Address initialize command. The third byte 0x85 assigns the first device address to 8. Then, the master device releases the bus and waits for the reply from the sensor. Each temperature sensor on the SMAART wire bus interface replies with the assigned 5-bit address (bytes 0x83, 0x8B). See the Communication Protocol section in the TMP107-Q1 Automotive Grade, ±0.4°C Temperature Sensor with Daisy-Chain UART, EEPROM, and Alert Function Data Sheet, for details.

Figure 1-2 shows an example of interfacing the TMP107-Q1 temperature sensor. The TXD signal drives the enable pin of the buffer instead of driving the input. This implementation converts the push-pull output to open drain (open collector). The 4.7-kΩ pullup resistor brings the bus to logic 1 during standby. The SMAART wire bus interface transfers data reliably up to 300 meters. This also means that the parasitic inductance of the signal wire and mismatched impedance may cause ringing and overshoots. The 100-Ω resistor protects the RXD input from damage by reducing the current through the integrated ESD protection diodes during transient events below GND and above VCC rail. The 10-Ω resistor eases signal collisions and slows down signal edges. This improves signal integrity.

Although the SMAART wire bus interface is proven to be reliable, both the CAN and RS-485 physical layers offer a significant improvement in noisy environments due to differential signaling. The difference between the CAN and RS-485 transceiver is the way they drive the bus.

The CAN transceiver uses an open collector output and does not require any driver enable signal. Multiple transceivers transmitting at the same time ruin data integrity but there is not any excessive current flowing through the bus. The CAN bus defines a recessive and dominant state on the bus. These states represent logic values zero or one. Figure 2-1 shows the fundamentals. See the blog article ^[1] for further details.

The RS-485 transceiver uses a push-pull configuration and requires a driver enable (DE) and receive enable (~RE) signal for direction control. The bus driver either actively drives the bus or enters the idle mode. In the idle mode the driver represents high impedance and external or internal fail-safe biasing ensures a default logic value of the bus. Any active driver can override the bus in the idle mode. In the active mode the push-pull driver controls nodes A and B. The differential voltage between the pins is positive or negative. The polarity of the differential voltage represents logic values on the bus. Higher voltage on the node A than on B represents
logic 1. Lower voltage on the node A than B represents logic 0.

Multiple RS-485 transceivers transmitting at the same time cause bus contention. One transceiver may force the signal line high whereas the second forces it low. Modern transceivers use protections but this unwanted event causes excessive power dissipation and ruins data integrity. Figure 2-2 shows fundamentals of the RS-485 bus. See the blog^[2] for additional information on RS-485 bus.

The CAN transceiver has dedicated pins for receiving (RXD) and transmitting (TXD) data. The TMP107-Q1 sensor has a single bidirectional pin (I/O). Connecting the bidirectional pin I/O directly to the RXD and TXD pins is not possible. The CAN transceiver has an internal loopback that mirrors all data on the CAN bus to the RXD pin. Merging RXD and TXD pins together would result in the bus conflict with undefined behavior.

Figure 3-1 shows a circuit that allows interfacing the TMP107-Q1 sensor over the CAN bus. Two logic buffers in IC2 convert the single bidirectional I/O signal to unidirectional RXD and TXD signals. Buffer enable pins 1OE and 2OE are complementary and share the same input signal (DIR). This means only one buffer is active at the same time. This functionality allows for data direction control and prevents the bus conflict due to the loopback mechanism in the CAN transceiver IC1. When the DIR signal is low, the TMP107-Q1 sensor IC3 listens to the CAN bus. When the DIR signal is high, the sensor transmits data to the master device over the CAN bus.

The TMP107-Q1 device does not have any dedicated pin that indicates receiving or transmitting state. An external circuit detects when the sensor needs to send data and toggles the buffer IC2 accordingly. The external circuit uses the industry standard 555 timer. Alternatively an analog comparator can perform the same functionality.

The detection mechanism uses different voltage levels for the logic 0 on the SMAART wire bus interface. Only the logic 0 is important because this corresponds to the dominant state on the CAN bus.

Logic zero from the CAN bus to the SMAART wire™ bus interface

Careful selection of resistors R3, R5, R6 ensures that a logic zero on the 1Y pin of IC2 never causes voltage on the TRIG pin of the IC4 reaching the triggering threshold VCC/3. Additionally, a proper combination of resistors R3, R6 sets the voltage on the SMAART wire bus interface below the low-level input voltage (VIL) threshold. This way the sensor still detects logic 0.

Logic zero from the SMAART wire™ bus interface to the CAN bus

The TMP107-Q1 device asserts logic 0. This factors out the resistor R3 and voltage on the TRIG pin reaches the triggering threshold VCC/3. The OUT pin of the IC4 toggles high and enables the buffer IC2 for transmission. Without the optional capacitor C1 the output remains high only as long as the TRIG signal is below the threshold. This means that the pull-up resistor R2 maintains logic 1 on the TXD pin. The capacitor C1 can extend the OUT pulse duration for the complete frame. This is beneficial for higher transfer speeds when the pull-up resistor R2 may not be able to quickly bring the TXD pin to logic 1.

Figure 3-2 shows example waveforms for the CAN to SMAART wire interface converter circuit from Figure 3-1.

Figure 4-1 shows the implementation with the RS-485 transceiver. The transceiver features complementary enable signals for the transmitter and the receiver. This integrated functionality replaces the SN74LVC2G241 buffer from the CAN-based circuit. For this reason, the DIR signal from the TLC555-Q1 timer connects directly to the DE and ~RE signals.

Figure 4-2 represents ideal waveforms for the circuit with the RS-485 transceiver.