SBOA542 November 2022 TMP1826 , TMP1827
All communication to the TMP1826 on the single-wire begins with the bus reset and response phase. The phase is initiated by the host by holding the single-wire data line low for a period of tRSTL. All devices on the bus, irrespective of their current state respond to the bus reset, by reinitializing their internal state and responding to the host-initiated bus reset. The devices respond after a minimum of tPDH, by holding the single-wire low for a time period of tRSTH as shown in Figure 1-2.