SBOA542 November   2022 TMP1826 , TMP1827

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Bus Reset and Response
    2. 1.2 Host Write, Device Read
    3. 1.3 Host Read, Device Write
  4. 2Interfacing TMP1826 With the Host MCU
    1. 2.1 Using GPIO as Host Interface
    2. 2.2 Software Driver for GPIO
    3. 2.3 Using UART as Host Interface
    4. 2.4 Software Driver for UART
    5. 2.5 Using SPI as Host Interface
    6. 2.6 Software Driver for SPI
  5. 3Summary
  6. 4References

2.3 Using UART as Host Interface

Universal Asynchronous Receiver Transmitter (UART) is also a common peripheral found on most MCUs. UART is a full-duplex asynchronous bus protocol with a transmit and receive function that are independent. The transmit function is a push-pull pin. Figure 2-6 shows that by using a push pull to open-drain converter and an external pullup resistor, the transmit function can be connected to the single-wire interface. The receive pin can then be tied to the same interface for reading bus reset response and data back from the single-wire devices.

Figure 2-6 UART Interface for TMP1826

The UART bus has a well-defined frame format. The frame itself consists of a mandatory start bit, variable number of data bits, an optional parity, and one or two stop bits. For interfacing the UART peripheral from a host MCU to the single wire bus, use the 8-N-1 format, where there is a start bit, followed by 8 data bits, no parity and 1 stop bit as shown in Figure 2-7.

Figure 2-7 UART Frame Structure

Figure 2-8 shows that the UART baud rate is set to 187.5kbps and the host transmits 0h00 for bus reset and receives 0hFC or 0hFE for a bus reset response.

Figure 2-8 UART Frame Overlay for Overdrive Bus Reset and Response

When writing to the devices, the UART baud rate is set to 500kbps and transmits 0hC0 for a logic '0' and 0hFF for a logic '1'.

Figure 2-9 UART Frame Overlay for Overdrive Write

When reading from the devices, the UART baud rate is set to 500kbps and transmits 0hFF. If the device sends a logic '0', the host on the receive pin can read the data as 0hFC or 0hF8. However if the device sends a logic '1', the host reads the data as 0hFF or 0hFE.

Figure 2-10 UART Frame Overlay for Overdrive Read

Table 2-1 provides the reference baud rates required by bus reset and data bits for standard and overdrive bus speed.

Table 2-1 UART Baud to Single-Wire Bus Speed
UART Baud for Single-Wire Standard Speed UART Baud for Single-Wire Overdrive Speed
Bus Reset Data Bit Bus Reset Data Bit
18750bps 115200bps 187500bps 500000bps