The PGA855 is a precision, wide-bandwidth programmable gain instrumentation amplifier with fully differential outputs optimized to drive high-performance analog-to-digital converters (ADCs) with fully differential inputs. The PGA855 is equipped with eight binary gain settings, from an attenuating gain of 0.125V/V to a maximum of 16V/V, using three digital gain-selection pins. The low-noise current-feedback front-end architecture offers excellent gain flatness, even at high frequencies, making the PGA855 an excellent high-impedance sensor readout device. Integrated protection circuitry on the input pins handles overvoltages up to ±40V beyond the power supply voltages. The PGA855 offers an excellent combination of AC performance and DC accuracy, making the PGA855 a versatile choice for a variety of sensors.
This application note shows the AC performance of the PGA855 driving the ADS127L11 and ADS127L21 delta-sigma ADCs. The focus of this document is on intrinsic noise, signal-to-noise ratio (SNR) and effective resolution performance. In particular, this application note provides guidelines of the analog filter selection and provides the performance of the PGA855 and ADS127Lx1 with different data rates and digital filter settings.
The document illustrates a step-by-step intrinsic noise analysis of the acquisition system, provides a calculator tool to estimate the system performance with different ADC digital filter and data rate settings, and shows the bench measurements of the PGA855 driving the ADS127Lx1.
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Analog signal acquisition in industrial systems is a challenging problem. Sensor output signals often present full-scale signals in the millivolt range, requiring resolutions in the microvolt range or even nanovolt range. The system designer's challenge is optimizing the sensor amplifier front-end to achieve the best signal to noise performance. Hence, understanding and minimizing these sources of noise is essential.
The instrumentation amplifier (INA) and the programmable gain instrumentation amplifier (PGA) are essential in industrial acquisition systems. These components offer high accuracy, low noise signal-conditioning and level shifting, and versatile gain programmability. INAs and PGAs offer a high-impedance front-end and have evolved into excellent ADC drivers in the back-end, offering a complete integrated signal acquisition design. Applications include industrial analog input modules measuring a wide variety of bridge, pressure, and temperature sensors; data acquisition cards; surgical equipment; vibration analysis, and power metering/battery testing systems.
Figure 7-13 shows a circuit example for the PGA855 driving the ADS127Lx1, a fully-differential input, high resolution, wide-bandwidth, delta-sigma ADC.
The PGA accepts single-ended or fully-differential input signals while driving the differential ADC inputs. Pin-controlled gains scale the input signal to the ADC input range. The super-beta input transistors offer a low input bias current, providing a very low input current noise density of 0.3pA/√Hz, making the PGA855 a versatile choice for many sensor types.
The PGA855 offers independent input and output power supplies. In this example, ±15V input power supplies are used for the PGA input section, allowing a wide voltage input range. The output stage is powered with the ADC 5V power supply. The 5V output stage supply operation prevents overloading the ADC inputs during PGA overdrive conditions. The VCM output pin of the ADC drives the PGA855's VOCM pin setting the common mode voltage of the PGA outputs.
The goal of the circuit on Figure 7-13 is to provide a high level of SNR and total harmonic distortion (THD) performance for a given circuit bandwidth requirement. The effective bandwidth of the circuit is affected by the PGA855 analog front end bandwidth as well as the ADC digital filter.
The PGA855 analog-front-end circuit consists of three analog filters. Figure 7-13 shows the filters of the PGA855-ADS127Lx1 circuit.
The first analog filter located at the input of the PGA helps reduce electromagnetic interference (EMI) and radio frequency interference (RFI) high-frequency extrinsic noise. This input filter can be customized per the application bandwidth and anti-aliasing requirements.
This circuit example uses a filter with the capacitor ratio of CIN_DIFF = 10 × CIN_CM. Using the 10-to-1 ratio for differential capacitor CIN_DIFF versus common-mode capacitors CIN_CM offers good differential and common-mode noise rejection. This ratio of capacitor values also tends to be less sensitive to the tolerance variation and mismatch of the filter capacitors. When the CIN_DIFF capacitor value is chosen to be 10 times larger than the common-mode capacitors, the resulting differential filter provides a corner frequency that is 20 times lower than the common-mode filter corner frequency. Therefore, differential signals are attenuated at a lower frequency than the common-mode signals. The instrumentation amplifier amplifies differential signals and rejects the common-mode voltage signals. Providing this ratio of capacitors helps to mitigate the effects due to the mismatch of the common-mode capacitors, where the asymmetric noise attenuation caused by the common-mode capacitor mismatch is attenuated to insignificant levels. By simple inspection, derive Equation 1 and Equation 2 to calculate the corner frequencies:
EMI/RFI input filter differential-mode corner frequency:
EMI/RFI input filter common-mode corner frequency:
Equation 1 provides an input differential filter f-3dB corner frequency of 7.58MHz. When measuring bridge sensors with high-resistance, the sensor resistance can affect the corner frequency of the input filter.
The second filter helps to limit the PGA855 intrinsic noise contribution, and works as a low-pass anti-aliasing filter. Typically, the bandwidth of the feedback filter can be adjusted per the application bandwidth requirements. This filter is implemented with the feedback capacitor, CFB, in parallel with the PGA855 output-stage 5kΩ feedback resistors forming a 1st order filter.
The PGA855 circuit bandwidth is limited by CFB. In this example, CFB is set to 47pF, in parallel with the output-stage 5kΩ feedback resistor providing a typical f–3dB corner frequency of 677kHz.
Note that the PGA855 internal fully differential amplifier output stage resistors, although precisely ratio-metrically matched among each other to provide very low gain error, can exhibit a ±15% absolute resistance over process and temperature variation, and this resistor variation must be taken in to account when implementing the noise filtering. The f–3dB corner frequency for the feedback filter can vary in the range of approximately 589kHz to approximately 677kHz when accounting for the 5kΩ ±15% absolute resistance variation of the internal feedback resistors.
The third differential R-C-R filter at the ADS127Lx1 inputs serves two purposes. First, the filter provides a third pole to the overall filter response, thereby increasing the filter rolloff slope. The filter also works as a charge reservoir to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion and low gain error that otherwise can degrade because of incomplete amplifier settling. The ADC input filter values are RFIL = 47.4Ω, CDIFF = 560pF, and CCM = 51pF. The ADS127Lx1 input precharge buffers significantly reduce the sample-and-hold input charge that raises the ADC input impedance to decrease gain error.
High-grade C0G (NP0) are used everywhere in the signal path (CIN_DIFF, CIN_CM, CFB, CDIFF, CCM) for low distortion. Among ceramic surface-mount capacitors, the type of dielectric used in C0G (NP0) capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
The PGA855 analog front-end circuit, accounting for all three analog filters, provides a nominal f–3dB bandwidth of 620kHz. On the high side of the internal 5kΩ feedback resistor tolerance, the PGA855 f–3dB bandwidth changes to 547kHz and the circuit maintains –0.1dB flatness to 85kHz. Figure 2-2 shows the TINA-TI simulated PGA855 AC frequency response.
The ADS127L11 and ADS127L21 is a family of wide-bandwidth, 24-bit, delta-sigma (ΔΣ) ADCs offering an excellent combination of AC performance and DC precision. These ΔΣ ADCs offer configurable digital filters to optimize for wideband or low latency operation, allowing wideband ac performance or for data throughput dc signals. The ADS127L11 supports data rates up to 400kSPS using the wideband filter and up to 1067kSPS using the low-latency (sinc4) filter. The ADS127L21 supports data rates up to 512kSPS using the wideband filter and up to 1365kSPS using the low-latency (sinc4) filter. The ADS127L21, in addition to the wideband and low latency filter options, it offers programmable infinite and finite impulse response (IIR and FIR) digital filters allowing custom filter profiles.
For a complete table of the available ADS127L21 and ADS127L11 digital filter (wideband, sinc4, sinc3, cascaded sinc3 + sinc1, and cascaded sinc4+sinc1) options, filter bandwidth specifications and noise performance, refer to the ADS127L21 and ADS127L11 device data sheets.
Table 7-6 shows an excerpt of the ADS127L21 sinc4 filter performance. In this example, the ADS127L21 is operated in high-speed mode, oversampling ratio, OSR = 64, sinc4 filter providing a data rate of 200kSPS. This corresponds to an input-referred noise of 5.53µVRMS and a f–3dB corner frequency of 45.5kHz for the sinc4 filter for these specific settings.
OSR | DATA RATE (kSPS) | –3-dB FREQUENCY (kHz) | ADC Noise (EnADC) (µVRMS) |
---|---|---|---|
HIGH-SPEED MODE (fCLK = 25.6MHz) | |||
12 | 1066.6 | 242.6 | 66.6 |
16 | 833 | 182 | 24.5 |
24 | 533.3 | 91.0 | 10.3 |
32 | 400 | 45.5 | 8.06 |
64 | 200 | 45.5 | 5.53 |
128 | 100 | 22.75 | 3.89 |
256 | 50 | 11.375 | 2.74 |
512 | 25 | 5.687 | 1.93 |
1024 | 12.5 | 2.844 | 1.40 |
2048 | 6.25 | 1.422 | 0.995 |
4096 | 3.125 | 0.711 | 0.709 |
This section illustrates the noise analysis of the PGA855 circuit example. The analysis includes the intrinsic noise sources of the instrumentation amplifier including the interaction of the input current noise of the device and source or sensor resistance.
The PGA855 architecture consists of a high-speed current-feedback input stage with an internally matched gain resistor network, followed by a four-resistor, fully differential amplifier output stage. Eight preprogrammed binary gains, from 0.125V/V to 16V/V are selectable using gain-select pins A0, A1, and A2. Each amplifier in the circuit has a corresponding amplifier voltage noise and current noise contribution. In addition, each resistor in the gain resistor network has a thermal noise contribution element. Figure 7-13 shows a functional block diagram for the PGA855 and the noise sources.
In the case of the PGA855, the voltage noise contribution of the internal amplifiers and the thermal noise contributions from the internal gain resistor network are lumped into a single voltage noise source eNI. The input stage amplifier current noise is kept as a separate current noise source at the input of the PGA855. Since the resistor network changes of each gain setting, the PGA855 data sheet provides separate referred-to-input (RTI) voltage noise density specifications for each gain setting from 0.125V/V to 16V/V respectively. Figure 7-13 shows the simplified noise model of the PGA855.
The simplified PGA855 model uses a single stage model; where all the noise specifications are referred to the amplifier input. The input current noise remains constant across all gains. To refer the noise to the device output, the designer needs to multiply the input-referred noise by the PGA gain. Equation 4 provides the calculation of the output-referred noise, eN(RTO) as a function of the PGA gain, G.