For the left side header, pin 1 is at the top left corner pin (denoted as an X). The right side header has pin 1 (denoted as an X), which is at the top right corner. Table 2-1 shows the jumper configurations. Note: U1 refers to the signal pathway that connects to the U1 TMUX73XXF footprint.

Check the device-specific data sheet for the pin-out. For power (VDD or VSS) and ground (GND), lines connect shunts on the appropriate jumpers to short the U1 pin to the respective VDD, VSS, or GND line. For testing where control pins do not change state (such as the select or enable pin always being at a logic ‘1’ for the duration of testing), shunts can be connected on the appropriate jumpers to short the U1 control pins to VDD or GND. For the remaining I/O pins (VDD, VSS, and GND), signals can be applied using shunts in the same manner as before or the shunt can be removed and an external signal can be applied to the U1 pin of the jumper or the respective test point.

In cases where the tests require pull-up or pull-down resistors versus directly attaching the source to the respective U1 pin, all 16 generic pathways contain 0603 resistor pads to add these components. Table 2-2 shows the IDs.

During the evaluation of TMUX734X devices, it is recommended to use the shunts on J14 and J15 to connect the multiplexer’s VFP and VFN pins to the desired VFP/VFN threshold voltage. The VFP_V and VFN_V threshold supplies can be either powered through the J2 terminal block or connected directly to the VFP_V and VFN_V test points. Additionally, the fault flag voltage (VFF_V) can be connected and powered through the V_FF blue test point.

Now loads can be attached to the board. If a pull-down pad was unused, then this pad can now be used as a pad for a resistive load. There are also pads for capacitive loads for each of the 16 generic signal paths and 2 OVP Trigger Thresholds that can also be utilized. Table 2-3 shows the corresponding pad and jumper IDs.

Now that the loading is complete for the board, additional supply decoupling capacitance to ground can be added for the VDD or VSS lines. Table 2-4 shows the power supply decoupling capacitance for each VDD or VSS line. If the default capacitance is enough, then move on to step 8.

Finally, attach the supply signals (VDD, GND, or VSS) to the appropriate pins of the terminal block labeled J1. Power is now ready to be applied to the board. For test points, please see the next section.