Design Objective

Objective: Margin a DC/DC output to ±26% the nominal value.

Design Description

This circuit uses a four-channel buffered voltage output DAC to margin an inverting step-down DC/DC converter. A voltage margining circuit is used to trim, scale, or test the output of a power converter. Adjustable power supplies, such as low dropout regulators (LDOs), DC/DC converters, or switch-mode power supplies (SMPS) provide a feedback (FB) pin that is used, along with a resistive voltage divider, to control the desired output. A precision smart DAC, such as the DAC63204W or DAC53204W (DACx3204W), provides linear control of the power supply output by using a series resistor to inject current into the voltage divider. The DACx3204 have a general-purpose input (GPI) pin that allows the DAC output to be toggled between a high and low voltage output. This allows the DC/DC to be toggled within ±26% of the nominal output value. All register settings are saved using the integrated non-volatile memory (NVM), enabling the device to be used without runtime software, even after a power cycle or reset. This circuit can be used in applications such as LIDAR, virtual reality headsets, and OLED TVs.

Design Notes

1. The DACx3204W 12-Bit and 10-Bit, Quad Voltage and Current Output Smart DACs With Auto-Detected I2C, SPI, or PMBus® Interface in DSBGA Package data sheet recommends using a 100-nF decoupling capacitor for the VDD pin and a 1.5-µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal LDO. Place these capacitors close to the device pins.
2. Connect a 100-nF capacitor from the VREF pin to GND if the external reference is used. Ramp up the external reference after VDD. Connect a pullup resistor from the VREF pin to VDD if the external reference is not used. This example uses the internal reference and the VREF pin is pulled up to VDD with a 10-kΩ resistor.
3. The output voltage (V_OUT) of the TPS63710 when the DAC63204W is not connected or the current through the series resistor, R₃, is 0 A set by resistors R₁ and R₂. The TPS63710 uses an internal –700-mV reference voltage (V_FB) at the FB pin to determine V_OUT. The current through R₃ is 0 A when the DAC63204W output voltage (V_DAC) equals V_FB. The DAC63204W cannot output a negative voltage, so this design assumes that the DAC63204W output is always positive, and the TPS63710 is at the nominal output voltage when the DAC63204W is at midscale.
4. Choose R₃ so that V_DAC > –0.3 V when the DAC63204W is set to power-down mode. When the DAC63204W is configured in 10 kΩ to GND power-down mode, the 10-kΩ resistance creates a resistor divider with R₃. R₃ is chosen to be 200 kΩ in this example, making V_DAC equal to –0.038 V when in 10 kΩ to GND power down. Do not use Hi-z power-down mode when a negative voltage is connected to V_DAC.
5. Choose the current through R₂ (I_R2) so that the bias current into the FB pin of the TPS63710 is negligible. R₂ is calculated using:
   ${\mathrm{R}}_2=\frac{{\mathrm{V}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{I}}_{\mathrm{R}2}}$

   I_R2 is chosen to be 5.2 µA. The TPS63701 has an internal gain factor of 1/0.9 which makes the effective V_FB –778 mV. R₂ is calculated to be:

   ${\mathrm{R}}_2=\frac{\left|-778\mathrm{ }\mathrm{m}\mathrm{V}\right|}{5.2\mathrm{ }\mathrm{\mu }\mathrm{A}}=150\mathrm{ }\mathrm{k}\mathrm{\Omega }$
6. The nominal TPS63710 V_OUT is chosen to be –3.45 V when V_DAC is at midscale, or 0.91 V. The current sourced from the DAC63204W output is calculated by:
   ${\mathrm{I}}_{\mathrm{D}\mathrm{A}\mathrm{C}}=\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}-{\mathrm{V}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{R}}_3}$
   ${\mathrm{I}}_{\mathrm{D}\mathrm{A}\mathrm{C}}=\frac{910\mathrm{ }\mathrm{m}\mathrm{V}+778\mathrm{ }\mathrm{m}\mathrm{V}}{200\mathrm{ }\mathrm{k}\mathrm{\Omega }}\mathrm{ }=8.44\mathrm{ }\mathrm{\mu }\mathrm{A}\mathrm{ }$

   R₁ can be calculated to achieve the desired nominal V_OUT using:

   ${\mathrm{R}}_1=\frac{{\mathrm{V}}_{\mathrm{F}\mathrm{B}}-{\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}}{{\mathrm{I}}_{\mathrm{R}2}-{\mathrm{I}}_{\mathrm{D}\mathrm{A}\mathrm{C}}}$
   ${\mathrm{R}}_1=\frac{-0.778\mathrm{ }\mathrm{V}+3.45\mathrm{ }\mathrm{V}}{5.2\mathrm{ }\mathrm{\mu }\mathrm{A}\mathrm{ }+8.44\mathrm{ }\mathrm{\mu }\mathrm{A}}=196\mathrm{ }\mathrm{k}\mathrm{\Omega }$
7. The DAC63204W sinks or sources additional current through R₁ by adjusting V_DAC to achieve the desired margin. V_DAC is calculated by:
   ${\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}=\left({\mathrm{I}}_{\mathrm{R}2}-\frac{{\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}-{\mathrm{V}}_{\mathrm{F}\mathrm{B}}}{{\mathrm{R}}_1}\right)\times {\mathrm{R}}_3+{\mathrm{V}}_{\mathrm{F}\mathrm{B}}$

   V_DAC,MAX and V_DAC,MIN are configured to margin V_OUT by 26%. V_OUT low is –4.34 V and V_OUT high is –2.55 V

   ${\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C},\mathrm{M}\mathrm{A}\mathrm{X}}=\left(-5.2\mathrm{ }\mathrm{\mu }\mathrm{A}-\frac{-4.34\mathrm{ }\mathrm{V}+0.778\mathrm{ }\mathrm{V}}{196\mathrm{ }\mathrm{k}\mathrm{\Omega }}\right)\times 200\mathrm{ }\mathrm{k}\mathrm{\Omega }-0.778\mathrm{ }\mathrm{V}=1.82\mathrm{ }\mathrm{V}$
   ${\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C},\mathrm{M}\mathrm{I}\mathrm{N}}=\left(-5.2\mathrm{ }\mathrm{\mu }\mathrm{A}-\frac{-2.55\mathrm{ }\mathrm{V}+0.778\mathrm{ }\mathrm{V}}{196\mathrm{ }\mathrm{k}\mathrm{\Omega }}\right)\times 200\mathrm{ }\mathrm{k}\mathrm{\Omega }-0.778\mathrm{ }\mathrm{V}=0\mathrm{ }\mathrm{V}$
8. The DAC codes for V_DAC,MAX and V_DAC,MIN are stored in the DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers. V_DAC,NOM is stored in the DAC-X-DATA register. The codes programmed to these registers, in decimal, is calculated using:
   $\mathrm{D}\mathrm{A}\mathrm{C}\_\mathrm{C}\mathrm{O}\mathrm{D}\mathrm{E}=\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}\times 2^{12}}{{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}}$

   This design uses the internal 1.21-V reference with a gain of ×1.5 giving a full-scale voltage of 1.82 V. The equations become:

   $\mathrm{D}\mathrm{A}\mathrm{C}\_\mathrm{M}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{I}\mathrm{N}\_\mathrm{H}\mathrm{I}\mathrm{G}\mathrm{H}=\frac{1.82\mathrm{ }\mathrm{V}\times 2^{12}}{1.82\mathrm{ }\mathrm{V}}=4096\mathrm{d}$
   $\mathrm{D}\mathrm{A}\mathrm{C}\_\mathrm{D}\mathrm{A}\mathrm{T}\mathrm{A}=\frac{0.91\mathrm{ }\mathrm{V}\times 2^{12}}{1.82\mathrm{ }\mathrm{V}}=2048\mathrm{d}$
   $\mathrm{D}\mathrm{A}\mathrm{C}\_\mathrm{M}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{I}\mathrm{N}\_\mathrm{L}\mathrm{O}\mathrm{W}=\frac{0\mathrm{ }\mathrm{V}\times 2^{12}}{1.82\mathrm{ }\mathrm{V}}=0\mathrm{d}$

   The maximum output code for a 12-bit device is 4095 so the V_DAC,MAX becomes 1.819 V.

9. The TPS63710 requires that V_IN ≥ |V_OUT| / 0.7. The max V_OUT for this application is –4.34 V, so the minimum V_IN is 6.2 V. 10 V is used in this design.
10. Using a 1.21-V reference with a ×1.5 gain and the 12-bit DAC63204W, the LSB size, or step size between each code, is about 443 µV. Using the lowest reference voltage possible decreases the LSB size and thus maximizes the resolution of V_DAC,MAX and V_DAC,MIN.
11. The DAC63204W has a programmable slew-rate feature. The programmable slew is configured with the CODE-STEP-X and SLEW-RATE-X fields in the DAC-X-FUNC-CONFIG register. The programmable slew is only available when toggling between two values stored in the DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers.

    CODE-STEP-X defines the number of LSB steps used to transition from the starting code to the final output code. SLEW-RATE-X defines the time-period for each code step. The slew time is calculated by:

    ${\mathrm{t}}_{\mathrm{S}\mathrm{L}\mathrm{E}\mathrm{W}}=\mathrm{S}\mathrm{L}\mathrm{E}\mathrm{W}\_\mathrm{R}\mathrm{A}\mathrm{T}\mathrm{E}\times \mathrm{C}\mathrm{E}\mathrm{I}\mathrm{L}\mathrm{I}\mathrm{N}\mathrm{G}\left(\frac{\mathrm{M}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{I}\mathrm{N}\_\mathrm{H}\mathrm{I}\mathrm{G}\mathrm{H}\_\mathrm{C}\mathrm{O}\mathrm{D}\mathrm{E}-\mathrm{M}\mathrm{A}\mathrm{R}\mathrm{G}\mathrm{I}\mathrm{N}\_\mathrm{L}\mathrm{O}\mathrm{W}\_\mathrm{C}\mathrm{O}\mathrm{D}\mathrm{E}}{\mathrm{C}\mathrm{O}\mathrm{D}\mathrm{E}\_\mathrm{S}\mathrm{T}\mathrm{E}\mathrm{P}}+1\right)$

    This application uses a margin high code of 4095, margin low code of 0, SLEW-RATE of 1282 μs/LSB and a CODE-STEP of 1 LSB to achieve a 5.25-s slew time:

    ${\mathrm{t}}_{\mathrm{S}\mathrm{L}\mathrm{E}\mathrm{W}}=1282\mathrm{ }(\mathrm{\mu }\mathrm{s}/\mathrm{L}\mathrm{S}\mathrm{B})\times \mathrm{C}\mathrm{E}\mathrm{I}\mathrm{L}\mathrm{I}\mathrm{N}\mathrm{G}\left(\frac{4095-0}{1\mathrm{ }\mathrm{L}\mathrm{S}\mathrm{B}}+1\right)=5.25\mathrm{ }\mathrm{s}$
12. The GPIO pin can be configured as a digital input to switch the DAC63204W output between the margin high and margin low outputs with a programmable slew. The GPI-EN bit in the GPIO-CONFIG register enables the GPIO pin as an input. The GPI-CH-SEL field selects which channels are controlled by the GPI. The GPI-CONFIG field selects the GPI function. Write 0b1010 to the GPI-CONFIG field to configure the GPIO pin to trigger margin-high or margin-low functions.
    • A high on GPI sets the DAC output to V_DAC,MAX and the TPS63710 V_OUT to low, or –4.34 V. A low on GPI sets the DAC output to V_DAC,MIN and the TPS63710 V_OUT to high, or –2.55 V.
13. The DAC63204W can be programmed with the initial register settings described in the Register Settings section using I²C or SPI. Save the initial register settings in the NVM by writing a 1 to the NVM-PROG field of the COMMON-TRIGGER register. After programming the NVM, the device loads all registers with the values stored in the NVM after a reset or a power cycle.

Design Results

This schematic is used for the following design results of the DAC63204W. The V_DAC, V_OUT, and V_FB signals are measured on an oscilloscope at the test points marked on the schematic.

This plot shows the low-to-high transition of the DAC63204W output with the 5.25-s slew configured using the settings discussed in the Design Notes. The V_DAC output voltage slews from 0 V to 1.82 V which causes the TPS63710 V_OUT voltage to slew from –2.55 V to –4.34 V.

This plot shows the start-up behavior of the circuit. The 10-V TPS63710 supply and 5-V DAC63204W supply are switched on at the same time. The V_DAC output starts up to the nominal voltage of 910 mV. The TPS63710 V_OUT ramps to the nominal output of –3.45 V as the V_FB reference voltage starts up.

Register Settings

The following table shows an example register map for this application. The values given here are for the design choices made in the Design Notes section.

Pseudocode Example

The following shows a pseudocode sequence to program the initial register values to the NVM of the DAC63204W. The values given here are for the design choices made in the Design Notes section.

Pseudocode Example for DAC63204W

1:  //SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
2:  //Set gain setting to 1.5x internal reference (1.8 V) (repeat for all channels)
3:  WRITE DAC-0-VOUT-CMP-CONFIG(0x3), 0x08, 0x00
4:  //Power-up voltage output on all channels and enable the internal reference
5:  WRITE COMMON-CONFIG(0x1F),0x12, 0x49
6:  //Configure GPI for Margin-High, Low trigger for all channels
7:  WRITE GPIO-CONFIG(0x24), 0x01, 0xF5
8:  //Set slew rate and code step (repeat for all channels)
9:  //CODE_STEP: 1 LSB, SLEW_RATE: 1282 μs/step
10: WRITE DAC-0-FUNC-CONFIG(0x06), 0x00, 0x0D
11: //Write nominal DAC code (repeat for all channels)
12: //For a 1.8-V output range, the 12-bit hex code for 0.9 V is 0x800. With 16-bit left alignment, 
13: this becomes 0x8000
14: WRITE DAC-0-DATA(0x19), 0x80, 0x00
15: //Write DAC margin high code (repeat for all channels)
16: //For a 1.8-V output range, the 12-bit hex code for 1.8 V is 0xFFF. With 16-bit left alignment, 
17: this becomes 0xFFF0
18: WRITE DAC-0-MARGIN-HIGH(0x01), 0xFF, 0xF0
19: //Write DAC margin low code (repeat for all channels)
20: //The 12-bit hex code for 0 V is 0x000. With 16-bit left alignment, this becomes 0x0000
21: WRITE DAC-0-MARGIN-LOW(0x02), 0x00, 0x00
21: //Save settings to NVM
22: WRITE COMMON-TRIGGER(0x20), 0x00, 0x02

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Design References

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Additional Resources

• Texas Instruments, DAC63004WCSP-Evaluation Module
• Texas Instruments, DAC63004WCSP-EVM User’s Guide
• Texas Instruments, Precision Labs - DACs
• Texas Instruments, TPS63710EVM-811

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