SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Extended Scan Interface Interrupt Register 2
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved | ESIIS2x | Reserved | ESIIS0x | Reserved | ESIIFG8 | ||
| r0 | rw-0 | rw-0 | r0 | rw-0 | rw-0 | r0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ESIIFG7 | ESIIFG6 | ESIIFG5 | ESIIFG4 | ESIIFG3 | ESIIFG2 | ESIIFG1 | ESIIFG0 |
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 14-13 | ESIIS2x | RW | 0h |
ESIIFG4 interrupt flag source 00b = ESIIFG4 is set with each count of ESICNT2. 01b = ESIIFG4 is set if (ESICNT2 modulo 4) = 0. 10b = ESIIFG4 is set if (ESICNT2 modulo 256) = 0. 11b = ESIIFG4 is set when ESICNT2 decrements from 01h to 00h. |
| 12 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 11-10 | ESIIS0x | RW | 0h |
ESIIFG7 interrupt flag source 00b = ESIIFG7 is set with each count of ESICNT0. 01b = ESIIFG7 is set if (ESICNT0 modulo 4) = 0. 10b = ESIIFG7 is set if (ESICNT0 modulo 256) = 0. 11b = ESIIFG7 is set when ESICNT0 increments from FFFFh to 00h. |
| 9 | Reserved | R | 0h |
Reserved. This bit is always read as zero and, when written, does not affect the bit setting. |
| 8 | ESIIFG8 | RW | 0h |
ESIIFG8 is set by one of the AFE2’s ESIOUTx outputs selected with the ESIIFGSET2x bits. 0b = No interrupt pending 1b = Interrupt pending |
| 7 | ESIIFG7 | RW | 0h |
ESI interrupt flag 7. ESIIFG7 is set at different count intervals of the ESICNT0 counter, selected with the ESIIS0x bits. ESIIFG6 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 6 | ESIIFG6 | RW | 0h |
ESI interrupt flag 6. This bit is set when the PSM transitions to a state with a set Q7 bit. ESIIFG6 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 5 | ESIIFG5 | RW | 0h |
ESI interrupt flag 5. This bit is set when the PSM transitions to a state with a set Q6 bit. ESIIFG5 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 4 | ESIIFG4 | RW | 0h |
ESI interrupt flag 4. This bit is set by the ESICNT2 counter conditions selected with the ESIIS2x bits. ESIIFG4 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 3 | ESIIFG3 | RW | 0h |
ESI interrupt flag 3. This bit is set by the ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers. ESIIFG3 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 2 | ESIIFG2 | RW | 0h |
ESI interrupt flag 2. This bit is set at the start of a TSM sequence generated by the divided ACLK. A TSM sequence started with ESISTART bit does not set ESIIFG2. ESIIFG2 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 1 | ESIIFG1 | RW | 0h |
ESI interrupt flag 1. This bit is set by the rising edge of the ESISTOP(tsm) signal. ESIIFG1 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |
| 0 | ESIIFG0 | RW | 0h |
ESI interrupt flag 0. This bit is set by the AFE1's ESIOUTx conditions selected by the ESIIFGSET1x bits. ESIIFG0 must be reset with software. 0b = No interrupt pending 1b = Interrupt pending |