SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Table 8-3 lists the memory-mapped registers for the FRCTL_A. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified.
The password defined in the FRCTL0 register controls access to all FRAM Controller A registers. When the correct password is written, write access to the registers is enabled. The write access is disabled by writing a wrong password in byte mode to FRCTL0 upper byte. Word accesses to FRCTL0 with a wrong password triggers a PUC. A write access to a register other than FRCTL0 while write access is not enabled causes a PUC.
Note 1: The correct password (A5h) is written to the FRCTLPW bits by the bootcode during the device boot-up process; therefore, the FRCTL0 (low byte), GCCTL0, and GCCTL1 registers are unlocked after the device is powered up or reset (BOR) or after LPMx.5 wakeup.
Note 2: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
| Offset | Acronym | Register Name | Type | Reset | Section |
|---|---|---|---|---|---|
| 0h | FRCTL0 | FRAM Controller A Control Register 0 | Read-Write | 9600h | Section 8.6.1 |
| 4h | GCCTL0 | General Control Register 0 | Read-Write | 4h | Section 8.6.2 |
| 6h | GCCTL1 | General Control Register 1 | Read-Write | 0h | Section 8.6.3 |