SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Memory Protection Unit Segmentation Access Management Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MPUSEGIVS | MPUSEGIXE | MPUSEGIWE | MPUSEGIRE | MPUSEG3VS | MPUSEG3XE | MPUSEG3WE | MPUSEG3RE |
rw-[0] | rw-[1] | rw-[1] | rw-[1] | rw-[0] | rw-[1] | rw-[1] | rw-[1] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPUSEG2VS | MPUSEG2XE | MPUSEG2WE | MPUSEG2RE | MPUSEG1VS | MPUSEG1XE | MPUSEG1WE | MPUSEG1RE |
rw-[0] | rw-[1] | rw-[1] | rw-[1] | rw-[0] | rw-[1] | rw-[1] | rw-[1] |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | MPUSEGIVS | RW | 0h |
MPU User Information Memory Segment Violation Select. This bit selects if additional to the interrupt flag a PUC must be executed on illegal access to User Information Memory 0b = Violation in User Information Memory asserts the MPUSEGIIFG bit and executes a SNMI if enabled by MPUSEGIE =1 1b = Violation in User Information Memory asserts the MPUSEGIIFG bit and executes a PUC |
14 | MPUSEGIXE | RW | 1h |
MPU User Information Memory Segment Execute Enable. If set, this bit enables execution on User Information Memory 0b = Execute code on User Information Memory causes a violation 1b = Execute code on User Information Memory is allowed |
13 | MPUSEGIWE | RW | 1h |
MPU User Information Memory Segment Write Enable. If set, this bit enables write access on User Information Memory 0b = Write on User Information Memory causes a violation 1b = Write on User Information Memory is allowed |
12 | MPUSEGIRE | RW | 1h |
MPU User Information Memory Segment Read Enable. If set, this bit enables read access on User Information Memory 0b = Read on User Information Memory causes a violation if MPUSEGIWE=MPUSEGIXE=0 1b = Read on User Information Memory is allowed |
11 | MPUSEG3VS | RW | 0h |
MPU Main Memory Segment 3 Violation Select. This bit selects if additional to the interrupt flag a PUC must be executed on illegal access to Main Memory segment 3 0b = Violation in Main Memory Segment 3 asserts the MPUSEG3IFG bit and executes a SNMI if enabled by MPUSEGIE =1 1b = Violation in Main Memory Segment 3 asserts the MPUSEG3IFG bit and executes a PUC |
10 | MPUSEG3XE | RW | 1h |
MPU Main Memory Segment 3 Execute Enable. If set this bit enables execution on Main Memory segment 3 0b = Execute code on Main Memory Segment 3 causes a violation 1b = Execute code on Main Memory Segment 3 is allowed |
9 | MPUSEG3WE | RW | 1h |
MPU Main Memory Segment 3 Write Enable. If set this bit enables write access on Main Memory segment 3 0b = Write on Main Memory Segment 3 causes a violation 1b = Write on Main Memory Segment 3 is allowed |
8 | MPUSEG3RE | RW | 1h |
MPU Main Memory Segment 3 Read Enable. If set this bit enables read access on Main Memory segment 3 0b = Read on Main Memory Segment 3 causes a violation if MPUSEG3WE = MPUSEG3XE = 0 1b = Read on Main Memory Segment 3 is allowed |
7 | MPUSEG2VS | RW | 0h |
MPU Main Memory Segment 2 Violation Select. This bit selects if additional to the interrupt flag a PUC must be executed on illegal access to Main Memory segment 2 0b = Violation in Main Memory Segment 2 asserts the MPUSEG2IFG bit and executes a SNMI if enabled by MPUSEGIE =1 1b = Violation in Main Memory Segment 2 asserts the MPUSEG2IFG bit and executes a PUC |
6 | MPUSEG2XE | RW | 1h |
MPU Main Memory Segment 2 Execute Enable. If set this bit enables execution on Main Memory segment 2 0b = Execute code on Main Memory Segment 2 causes a violation 1b = Execute code on Main Memory Segment 2 is allowed |
5 | MPUSEG2WE | RW | 1h |
MPU Main Memory Segment 2 Write Enable. If set this bit enables write access on Main Memory segment 2 0b = Write on Main Memory Segment 2 causes a violation 1b = Write on Main Memory Segment 2 is allowed |
4 | MPUSEG2RE | RW | 1h |
MPU Main Memory Segment 2 Read Enable. If set this bit enables read access on Main Memory segment 2 0b = Read on Main Memory Segment 2 causes a violation if MPUSEG2WE = MPUSEG2XE = 0 1b = Read on Main Memory Segment 2 is allowed |
3 | MPUSEG1VS | RW | 0h |
MPU Main Memory Segment 1 Violation Select. This bit selects if additional to the interrupt flag a PUC must be executed illegal access to Main Memory segment 1 0b = Violation in Main Memory Segment 1 asserts the MPUSEG1IFG bit and executes a SNMI if enabled by MPUSEGIE = 1 1b = Violation in Main Memory Segment 1 asserts the MPUSEG1IFG bit and executes a PUC |
2 | MPUSEG1XE | RW | 1h |
MPU Main Memory Segment 1 Execute Enable. If set this bit enables execution on Main Memory segment 1 0b = Execute code on Main Memory Segment 1 causes a violation 1b = Execute code on Main Memory Segment 1 is allowed |
1 | MPUSEG1WE | RW | 1h |
MPU Main Memory Segment 1 Write Enable. If set this bit enables write access on Main Memory segment 1 0b = Write on Main Memory Segment 1 causes a violation 1b = Write on Main Memory Segment 1 is allowed |
0 | MPUSEG1RE | RW | 1h |
MPU Main Memory Segment 1 Read Enable. If set this bit enables read access on Main Memory segment 1 0b = Read on Main Memory Segment 1 causes a violation if MPUSEG1WE = MPUSEG1XE = 0 1b = Read on Main Memory Segment 1 is allowed |