Raw Interrupt Status Register. Read Only Register.
Figure 22-29 SDHSRIS Register
15
14
13
12
11
10
9
8
ISTOP
Reserved
R-0h
R-0h
7
6
5
4
3
2
1
0
Reserved
WINLO
WINHI
DTRDY
SSTRG
ACQDONE
OVF
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 22-14 SDHSRIS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
ISTOP
R
0h
Incomplete Stop Raw Interrupt Status bit. Read Only. This bit is asserted when data conversion has been interrupted and stopped before completing the number of samples defined in SDHSCTL2.SAMPSZ.
This bit is offered only for polling the event by reading this bit. Interrupt is not available for this event. This bit must be de-asserted by writing '1' to SDHSICR.ISTOP bit.
Reset type: PUC
0h (R) = No ISTOP event
1h (R) = Conversion has been interrupted and stopped before completing the number of samples defined in SDHSCTL2.SAMPSZ.
14-6
Reserved
R
0h
Reserved. Always reads as 0.
5
WINLO
R
0h
SDHS Window Low Raw Interrupt Status bit. Read Only. This bit is asserted when output data value is lower than the value in the SDHSWINLOTH register.
Note:
1) The window comparator is only enalbed when SDHSCTL2.WINCMPEN = 1.
2) Note: It takes 4 system clock cycles + 4 sampling periods to update SDHSRIS.WINLO bit after the condition is detected.
Reset type: PUC
0h (R) = No new data is lower than the value in the SDHSWINLOTH register
1h (R) = New data is low than the value in the SDHSWINLOTH register
4
WINHI
R
0h
SDHS Window High Raw Interrupt Status bit. Read Only. This bit is asserted when the output data value is higher than the value in the SDHSWINHITH register.
Note:
1) The window comparator is only enalbed when SDHSCTL2.WINCMPEN = 1.
2) It takes 4 system clock cycles + 4 sampling periods to update SDHSRIS.WINHI after the condition is detected.
Reset type: PUC
0h (R) = No WINHI event
1h (R) = The output data value is higher than the value in the SDHSWINHITH register
3
DTRDY
R
0h
SDHS Data Ready Raw Interrupt Status bit. Read Only. This bit is asserted when a new conversion data is available in the data buffer and remains set as long as the buffer is not empty regardless of the SDHS data conversion status.
Note: the data buffer is automatically cleared when the data buffer becomes empty.
Following two methods can be used to empty the data buffer after completing data conversion if necessary:
1) When the DTC is enabled, no additional action is required. The DTC reads the data buffer until the data buffer becomes empty.
2) When the DTC is disabled, then either read the SDHSDT register until this bit is cleared or enable the DTC so that the DTC empties the buffer. Either way, this bit will be cleared when the buffer becomes empty.
Reset type: PUC
0h (R) = No DTRDY event
1h (R) = The data buffer has become empty.
2
SSTRG
R
0h
SDHS Conversion Start Trigger Raw Interrupt Status bit. Read Only.
Reset type: PUC
0h (R) = No SSTRG event
1h (R) = Converson Start signal has been asserted
1
ACQDONE
R
0h
Acquisition Done Raw Interrupt Status bit. Read Only. This bit is not de-asserted by hardware. This bit is asserted when data conversion is ended (either complete or incomplete).
If SDHSCTL2.DTOFF = 0, then this bit is asserted when data buffer becomes empty (i.e. when DTC completes the data transfer).
If SDHSCTL2.DTCOFF = 1, then this bit is asserted immediately when data conversion stops regardless of the data buffer status. In this case, CPU can continuously read the SDHSDT register until the data buffer becomes emtpy.
Reset type: PUC
0h (R) = No ACQDONE event
1h (R) = Data conversion has been finished (either complete or incomplete).
0
OVF
R
0h
SDHS Data Overflow Raw Interrupt Status bit. Read Only. This bit is not automatically de-asserted by hardware.
Reset type: PUC
0h (R) = No OVF event
1h (R) = When DTC is enabled (SDHSCTL2.DTCOFF = 0), DTC has dropped at least one sample. This indicates that the system clock needs to be increased.
When DTC is disabled (SDHSCTL2.DTCOFF = 1), At least one new sample has been overwritten to SDHSDT register before the previous value is read.