SLAU367P October 2012 – April 2020 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR5847 , MSP430FR58471 , MSP430FR5848 , MSP430FR5849 , MSP430FR5857 , MSP430FR5858 , MSP430FR5859 , MSP430FR5867 , MSP430FR58671 , MSP430FR5868 , MSP430FR5869 , MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5887 , MSP430FR5888 , MSP430FR5889 , MSP430FR58891 , MSP430FR5922 , MSP430FR59221 , MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5962 , MSP430FR5964 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR5969-SP , MSP430FR59691 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721 , MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR5989-EP , MSP430FR59891 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941 , MSP430FR6005 , MSP430FR6007 , MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430FR6820 , MSP430FR6822 , MSP430FR68221 , MSP430FR6870 , MSP430FR6872 , MSP430FR68721 , MSP430FR6877 , MSP430FR6879 , MSP430FR68791 , MSP430FR6887 , MSP430FR6888 , MSP430FR6889 , MSP430FR68891 , MSP430FR6920 , MSP430FR6922 , MSP430FR69221 , MSP430FR6927 , MSP430FR69271 , MSP430FR6928 , MSP430FR6970 , MSP430FR6972 , MSP430FR69721 , MSP430FR6977 , MSP430FR6979 , MSP430FR69791 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
Interrupt Enable Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Reserved | |||||||
r0 | r0 | r0 | r0 | r0 | r0 | r0 | r0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JMBOUTIE | JMBINIE | Reserved | NMIIE | VMAIE | Reserved | OFIE(1) | WDTIE(2) |
rw-0 | rw-0 | r-0 | rw-0 | rw-0 | r0 | rw-0 | rw-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | Reserved | R | 0h |
Reserved. Always reads as 0. |
7 | JMBOUTIE | RW | 0h |
JTAG mailbox output interrupt enable 0b = Interrupts disabled 1b = Interrupts enabled |
6 | JMBINIE | RW | 0h |
JTAG mailbox input interrupt enable 0b = Interrupts disabled 1b = Interrupts enabled |
5 | Reserved | R | 0h |
Reserved. Always reads as 0. |
4 | NMIIE | RW | 0h |
NMI pin interrupt enable 0b = Interrupts disabled 1b = Interrupts enabled |
3 | VMAIE | RW | 0h |
Vacant memory access interrupt enable 0b = Interrupts disabled 1b = Interrupts enabled |
2 | Reserved | R | 0h |
Reserved. Always reads as 0. |
1 | OFIE | RW | 0h |
Oscillator fault interrupt enable 0b = Interrupts disabled 1b = Interrupts enabled |
0 | WDTIE | RW | 0h |
Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is not necessary to set this bit for watchdog mode. Because other bits in SFRIE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instruction. 0b = Interrupts disabled 1b = Interrupts enabled |