SLLSE41H June   2010  – March 2016 SN75LVCP601

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Jitter and VOD Results: Case 1 at 6 Gbps
    2. 7.2 Jitter and VOD Results: Case 2 at 3 Gbps
    3. 7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Equalization
      2. 8.3.2 Output De-Emphasis
      3. 8.3.3 Out-of-Band (OOB) Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Equalization Configuration
        2. 9.2.2.2 De-emphasis Configuration
      3. 9.2.3 Application Curves
        1. 9.2.3.1 SN75LVCP601 Equalization Settings For Various Input Trace Lengths
        2. 9.2.3.2 SN75LVCP601 De-emphasis Settings For Various Output Trace Lengths
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from G Revision (January 2016) to H Revision

  • Changed pin DE1 number From: 8 To: 9 in the Pin Functions table Go
  • Changed pin DE2 number From: 9 To: 8 in the Pin Functions table Go

Changes from F Revision (June 2015) to G Revision

  • Changed Pin 8 name To: DE2 and Pin 9 name To: DE1 in Figure 27 Go

Changes from E Revision (January 2014) to F Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added Storage temperature to the Absolute Maximum Ratings tableGo
  • Moved timing parameters out of Electrical Characteristics and into Timing Requirements Go
  • Moved switching parameters out of Electrical Characteristics and into Switching Characteristics Go

Changes from D Revision (January 2013) to E Revision

  • Changed DJTX (UI = 333 ps) From: Max = 0.19 To: Max = 0.07Go
  • Changed DJTX (UI = 167 ps) From: Max = 0.34 To: Max = 0.16Go

Changes from C Revision (October 2012) to D Revision

  • Corrected formatting of the Differential output-voltage swing dc level section of the Electrical Characteristics tableGo

Changes from B Revision (February 2012) to C Revision

  • Deleted DiffVppTX rowGo
  • Inserted DiffVppTX_DE rowGo
  • Changed Figure 5 captionGo
  • Revised text of the Output Ed-Emphasis sectionGo
  • Deleted setting recommendations on pulse durations for DEW1 and DEW2Go

Changes from A Revision (October 2011) to B Revision

  • Changed pin type from CML to VML for pins 4, 5, 14, 15 in the Pin Functions tableGo

Changes from * Revision (June 2010) to A Revision

  • Changed pin EN number From: 4 To: 7 in the Pin Functions tableGo