Cell Balancing With BQ769x2 Battery Monitors

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1 Introduction

Cells are usually matched during the manufacturing of a battery pack. Over time, an imbalance in the state of charge may develop between cells and reduce the overall capacity of the pack. Cell balancing that equalizes the cells allows the pack to operate longer.

The BQ769x2 supports passive cell balancing by bypassing the current of selected cells during charging or at rest, using either integrated bypass switches between cells, or external bypass FET switches. The device incorporates a voltage-based balancing algorithm which can optionally balance cells autonomously without requiring any interaction with a host processor. Or if preferred, balancing can be entirely controlled manually from a host processor.

Due to the current that flows into the cell input pins on the BQ769x2 device while balancing is active, the measurement of cell voltages and evaluation of cell voltage protections by the device is modified during balancing. Balancing is temporarily disabled during the regular measurement loop while the actively balanced cell is being measured by the ADC, as well as when the cells immediately adjacent to the active cell are being measured. Similarly, balancing on the top cell is disabled while the stack voltage measurement is underway. This occurs on every measurement loop, and so can result in significant reduction in the average balancing current that flows. In order to help alleviate this, additional configuration bits are provided which cause the device to slow the measurement loop speed when cell balancing is active. The BQ769x2 device will insert current-only measurements after each voltage and temperature scan loop to slow down voltage measurements and thereby increase the average balancing current.

2 Cell Balancing Circuit Considerations

Cell balancing of a particular cell consists of enabling an integrated FET switch across the cell. The balancing current is determined by value of the input filter resistors selected when using internal balancing. FETs or BJTs can be used to increase the balance current in applications where the internal balancing current may not be sufficient. The next sections will discuss circuit design considerations for internal balancing, external balancing with N-channel FETs, external balancing with P-channel FETs, and external balancing with BJTs. Considerations for power dissipation and timing will also be discussed.

2.1 Internal Cell-Balancing Circuit Design

When one of the internal balance FETs is enabled, the internal FET will pull the pins for that cell together drawing current through the input resistors for that cell. The recommended minimum value of the input filter resistors when using internal balancing is 20 Ω. This value maximizes the balance current while keeping it well within the absolute maximum cell balancing current over the internal FET R_DS(ON) range. The maximum recommended value for the input filter resistors is 100 Ω.

The typical internal cell balancing resistance (R_DS(ON) for the internal FET) is 25 Ω. For a typical lithium ion cell with a full charge voltage of 4.2 V, this results in a balancing current of approximately 65 mA. This is the DC current if the switch was on continuously, so the average balancing current will be lower. The duty cycle is determined by a multiple factors is discussed in more detail in Section 5.

I_Balance = VCell / (2 x R_n + R_CB) = 4.2 V / (2 x 20 + 25) ~= 65 mA

Figure 2-1 Application Circuit for Internal Balancing

For many applications, the internal balancing current for the device is sufficient and additional external components are not required. However, one must consider the power dissipation and the resulting impact on the device temperature. For example 65 mA into 25 Ω results in about 0.1 W. The junction to ambient thermal resistance for the device is 66 °C/W. If 5 cells are balancing at the same time, this can result in a junction temperature rise of 33 °C.

There are multiple ways to avoid excessive power dissipation. The maximum number of cells allowed to balance simultaneously can be limited by setting Settings: Cell Balancing Config: Cell Balance Max Cells. There are also parameters to control when balancing is allowed based on the cell temperature or the internal temperature of the device. These parameters are available to control power dissipation and temperature in autonomous mode. The cell input resistors values can also be increased to reduce balancing current which will also reduce power dissipation.