SLUAA81A October   2020  – February 2022 BQ769142 , BQ76922 , BQ76942 , BQ76952

 

  1.   Trademarks
  2. 1Introduction
  3. 2Cell Balancing Circuit Considerations
    1. 2.1 Internal Cell-Balancing Circuit Design
    2. 2.2 External Cell-Balancing Circuit Design Using N-Channel FETs
    3. 2.3 External Cell-Balancing Circuit Design Using P-Channel FETs
    4. 2.4 External Cell-Balancing Circuit Design Using BJTs
    5. 2.5 Voltage Measurement Accuracy During Balance
  4. 3Stand-Alone Balancing Algorithm and Settings
  5. 4Considerations for a Host-Balancing Algorithm
  6. 5Timing Information
  7. 6Debugging Common Issues With Cell Balancing
    1. 6.1 Using a Resistor Divider as a Cell Simulator
  8. 7References
  9. 8Revision History

1 Introduction

Cells are usually matched during the manufacturing of a battery pack. Over time, an imbalance in the state of charge may develop between cells and reduce the overall capacity of the pack. Cell balancing that equalizes the cells allows the pack to operate longer.

The BQ769x2 supports passive cell balancing by bypassing the current of selected cells during charging or at rest, using either integrated bypass switches between cells, or external bypass FET switches. The device incorporates a voltage-based balancing algorithm which can optionally balance cells autonomously without requiring any interaction with a host processor. Or if preferred, balancing can be entirely controlled manually from a host processor.

Due to the current that flows into the cell input pins on the BQ769x2 device while balancing is active, the measurement of cell voltages and evaluation of cell voltage protections by the device is modified during balancing. Balancing is temporarily disabled during the regular measurement loop while the actively balanced cell is being measured by the ADC, as well as when the cells immediately adjacent to the active cell are being measured. Similarly, balancing on the top cell is disabled while the stack voltage measurement is underway. This occurs on every measurement loop, and so can result in significant reduction in the average balancing current that flows. In order to help alleviate this, additional configuration bits are provided which cause the device to slow the measurement loop speed when cell balancing is active. The BQ769x2 device will insert current-only measurements after each voltage and temperature scan loop to slow down voltage measurements and thereby increase the average balancing current.