SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

8.3 RLIM Single Output Configuration

When the UCC14240-Q1 is configured for single output VDD operation, there is no CVDD, CVEE capacitive divider, RLIM is applied as shown in Figure 8-7 and takes on a different role. During shutdown or VDD-VEE undervoltage fault, S2 is closed and RLIM provides a controlled discharge path for CVDD (and 2.2 µF // 0.1 µF) as shown by IDSCH. In this case, the minimum recommended RLIM value of 1 kΩ should be used to safely limit IDSCH through the internal lower pull down, RINT_DN.



Figure 8-7 RLIM, Single Output Configuration

As an example, using RLIM=1 kΩ, assuming CVDD=22 µF, VDD-VEE=20 V, the time it would take to discharge from the undervoltage fault detection threshold of 0.9x(VDD-VEE) down to 0.5 V would be ~91 ms, assuming there was no load present at VDD-VEE. Removing the charge on CVDD assures the UCC14240-Q1 will not restart into a pre-biased load.

Equation 35. tDSCH=-RLIM+RINT_DN×CVDD+2.2 μF×ln⁡VCtVDD-VEE×0.9=-1 kΩ+50 Ω×22 μF+2.2 μF×ln⁡0.5 V20 V-0 V×0.9≈91 ms