SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

8.1 RLIM Functional Description

To maintain accurate voltage regulation, charge mismatch between CVDD and CVEE, must be compensated by the UCC14240-Q1. This is accomplished by a simple, totem pole pair of asynchronous, internal switches depicted as S1 and S2 in Figure 8-1 and Figure 8-2. When the UCC14240-Q1 is configured for dual output, the primary purpose of the current limit resistor, RLIM, is to limit the peak current through S1 during VDD current source and S2 during VEE current sink. RLIM also has the secondary function of regulating the current necessary to maintain charge balance between CVDD and CVEE.

If the ideal CVDD to CVEE ratio were obtained, according to the voltage ratio outlined in the Section 7 section, then VDD-VEE is regulated, COM-VEE is indirectly regulated and ILIM=0 A. However, CVDD to CVEE capacitor value mismatch due to temperature, tolerance, aging and applied DC voltage inevitably result in capacitor variation between ideal and actual component values. In addition, the source and sink quiescent current, IQ, of the gate driver IC results in a small but significant charge imbalance between the CVDD to CVEE capacitor. The UCC14240-Q1 internal RLIM regulator helps to maintain tight voltage regulation better than 1.3% by compensating for errors caused by such instances.