SLUAAL2 june   2023 UCC256402 , UCC256403 , UCC256404

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UCC25640x Frequently Asked Questions
    1. 1.1  For the Time Domain Simulation and Fundamental Harmonic Analysis of LLC Resonant Converters, What Model of the Transformer Should be Used?
      1. 1.1.1 LLC Design Using T Type Transformer Model
    2. 1.2  How to Connect External Gate Drivers to the UCC25640x for High Gate Driver Current Capability?
    3. 1.3  When Powering on the PFC-LLC AC-DC Converter, What Sequence is Recommended?
    4. 1.4  How to Eliminate the Nuisance ZCS Detection During the Light Load?
    5. 1.5  What is the Purpose of Maintaining the FB Pin Voltage of the UCC25640x Controllers at a Constant Level?
    6. 1.6  How to Improve the Slew Rate Detection at HS Pin of the UCC25640x Controller?
    7. 1.7  How to Operate the UCC25640x Controller in the Open Loop?
    8. 1.8  What Happens if the VCR Pin Peak to Peak Voltage of the Controller Exceeds 6 V?
    9. 1.9  What UCC25640x settings effect the startup duration of the LLC?
    10. 1.10 What is Causing the Current Imbalance in the LLC's Secondary Side Windings?
    11. 1.11 How to Design TL431 Compensator for LLC With UCC25640x Controller
      1. 1.11.1 LLC Plant Transfer Function Under HHC Control
      2. 1.11.2 Type 2 and Type 3 Compensator with TL431 [20]
        1. 1.11.2.1 Type 2 Compensator
        2. 1.11.2.2 Type 2 Compensator Without Fast Lane
        3. 1.11.2.3 Type 3 Compensator with Fast Lane
        4. 1.11.2.4 Type 3 Compensator Without Fast Lane
      3. 1.11.3 Type 3 Compensator Design Example
    12. 1.12 How to Design LLC for Battery Charging and LED Driver Applications?
      1. 1.12.1 LED Driver Design Example
      2. 1.12.2 Battery Charger Design Example
    13. 1.13 How to Implement CC-CV Feedback Control?
      1. 1.13.1 Voltage Feedback Loop (Type 2) Transfer Function
      2. 1.13.2 Current Feedback Loop (Type 2) Transfer Function
    14. 1.14 What is the Simplest Approach to Configure the Burst Mode Thresholds for UCC25640x Based on the Load Power?
    15. 1.15 How to Avoid the UCC25640x Controller to Enter into Burst Mode?
    16. 1.16 What are the Methods for Preventing VCC From Decreasing Below the VCC Restart Threshold During Burst Mode?
    17. 1.17 How Does BMTL Threshold Value Impacts the Output Voltage Ripple and the VCC Pin Voltage and Magnetizing Current?
    18. 1.18 How to Design Magnetics for LLC?
      1. 1.18.1 LLC Resonant Inductor Design
      2. 1.18.2 LLC Transformer Design
    19. 1.19 How is the Dead Time in UCC25640x Determined During ZCS Detection and in the Absence of Valid Slew Rate Detection?
  5. 2References

Type 3 Compensator Design Example

The power stage of the UCC25640x EVM [3] is considered to demonstrate the Type 3 compensator [1.12.2.3] design which is shown in Figure 1-27. Lets consider 10kHz as a cross over frequency (fc) for the loop gain.

  1. From Figure 1-22, the open loop gain G p l a n t ( s ) = V o u t ( s ) F B r e p l i c a ( s ) is close to -25dB at 10kHz.
  2. So G c ( s ) should be 25dB at the cross over frequency.
  3. Assuming f L f z f c f p 2 f p 1 in [1.12.2.3], G c ( s ) can be approximated as G o f c f z . For a given phase lead ( θ ), cross over frequency ( f c ), fz, fp2 can be found out using following equations [Chapter 9.5 in Reference 9]: f c = f z f p 2 , f z = f c 1 sin ( θ ) 1 + sin ( θ ) , f p 2 = f c 1 + sin ( θ ) 1 sin ( θ ) . So, G c ( s ) G o f c f z = G o f z f p 2 f z = G o f p 2 f z .
  4. For a phase lead of 52o, fz and fp2 should be 3.4kHz and 29kHz respectively.
  5. Since fz, fp2 are found out, Go can be obtained using following expression: G o f p 2 f z = 17.78   G o = 6.126 (25dB=17.78).
  6. fp1 is a high frequency pole which is used to eliminate the high frequency noise. It is recommended to place this pole close to ESR of the output capacitor. Here fp1 is chosen as 479kHz.
  7. fL should be chosen such that controller should be able to regulate the output voltage when the converter operates in the burst mode. So, fL should be less than the burst mode frequency. In this design, fL is considered as 88Hz.
  8. Rup and Rlow can be found out using following expressions: V o V r e f R u p = I r e f + V r e f R l o w where Vo is output voltage and Vref, Iref are reference voltage and bias current through the reference pin of the shunt regulator. To make Vo independent of the Iref, the Iref should be much lower than V o V r e f R u p . So, V o V r e f R u p = V r e f R l o w . In the EVM, TLVH431 is considered for which reference voltage is given as 1.24V. For this design, V o V r e f R u p is considered as 73uA. So Rup obtained as 147kOhm. And from V o V r e f R u p = V r e f R l o w , Rlow obtained as 16.98kohm.
  9. Consider Cf as 10pF. So, Rv can be obtained as ω p 1 = 1 R v C f f p 1 = 1 2 π R v C f R v = 1 2 π 479 k H z C f R v = 33.2 k o h m
  10. RLED can be obtained as G o = R f b C T R R L E D 1 + R v R u p R L E D = R f b C T R G o 1 + R v R u p R L E D = 100 10 3 0.2 6.126 1 + 33.2 k 147 k R L E D = 4 k o h m
  11. Cv can be obtained as ω L =   1 R v + R u p C v C v = 1 2 π f L R v + R u p C v = 1 2 π 88 33.2 k + 147 k C v = 10 n F
  12. Cp, Rp are obtained as ω z =   1 R L E D + R p C p  ,    ω p 2 = 1 R p C p f z =   1 2 π R L E D + R p C p  ,   f p 2 = 1 2 π R p C p 3.4 k H z =   1 2 π R L E D + R p C p  ,   29kHz = 1 2 π R p C p C p = 10 n F  ,  R p = 540 o h m .
  13. Rbias is used to bias the shunt regulator. Rbias is obtained as R b i a s = V o p t o I b i a s = 1 V 1 m A = 1 k o h m .
GUID-20220830-SS0I-TSQJ-GFGQ-8QJ4ZBKFDSLM-low.png Figure 1-27 Type 3 Compensator