The PFC power stage shown in Figure 12-8 employs a 2-phase boost PFC topology, even though the default configuration of the EVM is single phase PFC. The power MOSFETs, Q3 and Q4, are driven by the controller’s DPWM signals, DPWM1B and DPWM2B, through UCC27324 MOSFET gate drive device. The schematic also shows that four additional signals are sensed and eventually connected to UCD3138 controller’s 12-bit ADC input pins. These four signals are the rectified AC line and neutral voltage, the DC bus voltage for voltage loop control, redundant OVP protection and input current. The sensed signals are scaled and conditioned to a range of 0 V to 2.5 V which corresponds to the full scale range of the ADC.

For single-phase PFC and 2-phase interleaved PFC, the PFC stage total input current is differentially sensed across the sense resistors, R6 and R7, and then conditioned by the current sense amplifier U1. This is shown in Figure 12-8. This sensed input current signal is scaled and conditioned to a range of 0 V to 1.6 V corresponding to the range of the on-chip DAC associated with the error ADC0 (EADC0).

In DCM mode, the inductor current oscillates between the inductor and switch node equivalent capacitor. As a result, the inductor current goes to negative, but the negative current will not show up at the output of the current amplifier. Therefore, the amplifier output does not represent the total inductor current. In order to sense this negative current, an offset is added to the amplifier’s positive input terminal, this is shown as R113 in Figure 12-8.

For bridgeless PFC, the PFC stage input current is sensed by current transformer T2 and T3. The output signal of T2 and T3 is rectified, scaled and conditioned to a range of 0 V to 1.6 V corresponding to the range of the on-chip DAC associated with the error ADC1 (EADC1) and error ADC2 (EADC2).

Figure 12-8 PFC Power Stage