SLUUBD5D September   2019  – February 2022 UCC12040 , UCC12050 , UCC12051-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
  4. 3Typical Application Circuit and Top Component View
  5. 4Pin Configuration and Pin Functions
    1. 4.1 Pin Functions
  6. 5EVM Setup and Operation
    1. 5.1 U1 Component Selection
    2. 5.2 External Connections for Easy Evaluation
    3. 5.3 High Voltage Isolation
    4. 5.4 Enabling and Disabling the UCC12050
    5. 5.5 SYNC and SYNC_OK Functionality
    6. 5.6 Output Voltage Selection
    7. 5.7 Test Points: TP1, TP2 & TP3
    8. 5.8 Board Level EMI Mitigation Techniques
  7. 6List of Materials
  8. 7Schematic
  9. 8Layout Diagrams
  10. 9Revision History

5.3 High Voltage Isolation

The UCC12050DVE is capable of supporting reinforced isolation. To this end, the PCB in the UCC12050DVE is designed to demonstrate proper layout techniques to enable reinforced isolation. The channel distance between the primary and secondary side (including the GNDP to GNDS planes and VINP to VISO distance) satisfies requirements for minimum required creepage and clearance distances to maintain reinforced isolation barrier between the input side to the output side.

Note:

This EVM is not intended for high voltage isolation testing, but merely to demonstrate proper isolation board design.