SLUUBD5D September   2019  – February 2022 UCC12040 , UCC12050 , UCC12051-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
  4. 3Typical Application Circuit and Top Component View
  5. 4Pin Configuration and Pin Functions
    1. 4.1 Pin Functions
  6. 5EVM Setup and Operation
    1. 5.1 U1 Component Selection
    2. 5.2 External Connections for Easy Evaluation
    3. 5.3 High Voltage Isolation
    4. 5.4 Enabling and Disabling the UCC12050
    5. 5.5 SYNC and SYNC_OK Functionality
    6. 5.6 Output Voltage Selection
    7. 5.7 Test Points: TP1, TP2 & TP3
    8. 5.8 Board Level EMI Mitigation Techniques
  7. 6List of Materials
  8. 7Schematic
  9. 8Layout Diagrams
  10. 9Revision History

5.5 SYNC and SYNC_OK Functionality

J3 is provided to connect an external clock to the UCC12050. In order to synchronize multiple UCC12050 devices to a single clock source, connect an external oscillator (a function generator) between SYNC and GNDP. The oscillator must be a 0 V to 5 V square wave at a frequency of double the desired switching frequency with a 50% duty cycle. The frequency must be within the specified operating range of the device, 14.4 MHz - 17.6 MHz.

The SYNC_OK output, J4, indicates when a valid clock source is connected to SYNC_OK. SYNC_OK is high impedance when a valid clock is connected, and pulled to GNDP when no clock, or an invalid clock, is connected to SYNC. SNYC_OK is pulled up to VINP on the EVM. R2 pads are available to place a termination resistor on SYNC, if needed.