SLUUBD5D September   2019  – February 2022 UCC12040 , UCC12050 , UCC12051-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
  4. 3Typical Application Circuit and Top Component View
  5. 4Pin Configuration and Pin Functions
    1. 4.1 Pin Functions
  6. 5EVM Setup and Operation
    1. 5.1 U1 Component Selection
    2. 5.2 External Connections for Easy Evaluation
    3. 5.3 High Voltage Isolation
    4. 5.4 Enabling and Disabling the UCC12050
    5. 5.5 SYNC and SYNC_OK Functionality
    6. 5.6 Output Voltage Selection
    7. 5.7 Test Points: TP1, TP2 & TP3
    8. 5.8 Board Level EMI Mitigation Techniques
  7. 6List of Materials
  8. 7Schematic
  9. 8Layout Diagrams
  10. 9Revision History

4.1 Pin Functions

PINI/O(1)DESCRIPTION
NAMENO.
EN1IActive-high enable input. Connect EN to GNDP to disable the device. Connect EN to VINP to enable the device. EN should be in the desired state (enabled/disabled) prior to power up.
GNDP2PGround return for primary side supply (VINP).
VINP3PPrimary side input supply voltage input. Connect a 10-μF ceramic capacitor between VINP and GNDP, close to the device pins, for proper operation. Connect a 0.1µF ceramic capacitor in parallel with the 10µF for additional high frequency filtering.
SYNC4ISynchronous clock input pin. Provide a clock signal to synchronize multiple UCC12050 devices or connect to GNDP for standalone operation using the internal oscillator. If the SYNC pin is left open it should be separated from any switching noise to avoid false clock coupling.
SYNC_OK5OActive-low, open-drain diagnostic output. Pin is asserted LOW if no external SYNC clock or one that is outside of the operating range of the UCC12050 is detected. In this state, the external clock is ignored and the DC/DC converter is clocked by the device's internal oscillator. The pin is in high-impedance if a good clock is applied on SYNC.
NC6, 7, 8—No internal connection. Connect NC to GNDP on printed circuit board.
GNDS9, 15, 16PGround return for secondary side (VISO).
NC10, 11, 12—No internal connection. Connect NC to GNDS on printed circuit board.
SEL13IVISO regulation voltage selection input. VISO regulation is selectable between 3.3V, 3.7V, 5.0V, and 5.4V using the SEL input. See for more details using SEL to select the VISO regulation threshold.
VISO14PIsolated supply voltage output. Connect a 10-μF ceramic capacitor between VISO and GNDS, close to the device pins, for proper operation. Connect a 0.1µF ceramic capacitor in parallel with the 10µF for additional high frequency filtering.
(1) P = Power, G = Ground, I = Input, O = Output