SLUUCL4A August   2022  – March 2023 TPS563252 , TPS563257

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Performance Specification Summary
  5. 3Output Voltage Setpoint
  6. 4Test Setup and Results
    1. 4.1 Input and Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Efficiency
    4. 4.4 Load Regulation
    5. 4.5 Line Regulation
    6. 4.6 Load Transient Response
    7. 4.7 Start-Up
    8. 4.8 Shutdown
    9. 4.9 Output Voltage Ripple
  7. 5Board Layout
    1. 5.1 Layout
  8. 6Schematic, List of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 List of Materials
    3. 6.3 Reference
  9. 7Revision History

4.1 Input and Output Connections

The TPS563252EVM is provided with input and output connectors and test points as shown in Table 4-1. Figure 4-1 shows connectors and jumpers placement on the TPS563252EVM board.

A power supply capable of supplying 3 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J2 through a pair of 20-AWG wires. The maximum load current capability is 3 A. Wire lengths must be minimized to reduce losses in the wires. Test point TP2 provides a place to monitor the VIN input voltages with TP6 providing a convenient ground reference. TP3 is used to monitor the output voltage with TP10 as the ground reference.

GUID-20230306-SS0I-89KX-R23F-ZM3ZSX57MHNC-low.svg Figure 4-1 TPS563252EVM Connectors and Jumpers Placement
Table 4-1 Connection and Test Points
Reference Designator Function
J1 VIN (see Table 1-1 for VIN range)
J2 VOUT, 1.05 V at 3-A maximum
JP1 EN control. Shunt EN to GND to disable.
JP2 Source selection for PGOOD
TP1 VIN positive power point
TP2 VIN positive monitor point
TP3 VOUT positive monitor point
TP4 VOUT positive power point
TP5, TP7 GND power point
TP6, TP10, TP12, TP13, TP16 GND monitor point
TP8 Switch node test point
TP9 EN test point
TP11 Test point for loop response measurements
TP14 PGOOD test point
TP15 External VCC point