SLVAE09B July   2018  – August 2021 TPS560430

 

  1.   Trademarks
  2. 1Introduction
  3. 2Peak Current Mode Loop Modeling
    1. 2.1 Overall Control Block Diagram and Transfer Function Derivation
    2. 2.2 Inside Current Loop Model
    3. 2.3 Overall Loop Model
    4. 2.4 Inductor and Output Capacitor Design Limits
    5. 2.5 The Equation to Calculate Bandwidth and Phase Margin
  4. 3Inductor and Output Capacitor Design
    1. 3.1 Inductor Design
    2. 3.2 Output Capacitor Design
    3. 3.3 Simulation and Bench Verification
  5. 4Summary
  6. 5References
  7. 6Revision History

1 Loop Response Considerations in Peak Current Mode Buck Converter Design

The internal loop compensated Peak Current Mode (PCM) buck converter is popular. The loop response is good for normal inductor and output capacitor design, but improper inductor and output capacitor values can lead to instability or bad transient performance. This application report details the PCM buck converter, analyzes the stability constraint, and provides a simple equation to calculate bandwidth and phase margin of the converter.

The model proposed in this application report is introduced in Section 1. Section 2 provides peak current mode loop modeling. The inside current loop is simplified as a single pole. The overall loop response transfer function is obtained. The inductor and output capacitor design limits are derived considering loop response. At the end of this section, the equation to calculate bandwidth and phase margin is provided. In Section 3, the inductor and output capacitor is designed step-by-step considering loop response. The theory is verified by simulation and bench measurement results.