SLVAEP4 October   2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Receiver Topology and Common Mode Voltages
  6. Signal Integrity Requirements
    1. 3.1 Receiver Timing Requirements
    2. 3.2 Receiver Threshold Requirements
  7. Debug Fault Registers
  8. Isolation Types
    1. 5.1 Transformer Isolation
    2. 5.2 Capacitor Only Isolation
    3. 5.3 Capacitor and Choke Isolation
  9. Mixed Isolation Circuits using bq79600-Q1
  10. Ring Architecture
  11. Noise Immunity and Emissions
  12. Daisy Chain Cable Selection
  13. 10References

Receiver Timing Requirements

As shown in Figure 3-3, the high and low timing differs between a tone signal (1us pulse width at 500 kHz) or data communications (approximately 250 ns pulse width at 2 MHz) waveform. However, both tones and data communications share similar rise/fall times and must both be rectangular waveforms with a maximum decay below 1 V. Note that the timing for the thigh/tlow refers to the time that the signal must be above or below the proper threshold value for the integration to succeed. If the signal is noisy during this thigh/tlow time and droops below the threshold value for some time - then there is risk of the signal being detected. We expect that roughly 1us ± 8% for tones and 250ns ± 20ns for data communications is the allowed timing variation for these signals to still be properly detected.