1 Introduction

For the power of signal processing system design utilizing ADCs, PLLs and RF transceivers, low output voltage ripple is an important factor for power quality evaluation. In some power design designed to achieve low output voltage ripple, normally a buck converter is used for voltage step down as first stage and an LDO is used to filter ripple as second stage. However, the BOM cost, design size and conversion efficiency can cause concern in some compact or cost-effective application.

In recent years, a new low ripple power design attracts more attention by using a secondary stage passive LC filter combined with buck converter. Compared with conventional design with LDO, reduced design size and efficiency improvement can be achieved. See Powering the AFE7920 with the TPS62913 Low-Ripple and Low-Noise Buck Converter application note. But a pair of conjugate poles can be introduced by the added passive filter, which threatens the loop stability. To overcome the challenge, some buck converters are designed with unique internal compensation to support second stage LC filter, such as TPS62912/3 and TPSM82912/3 known as low noise and low ripple power design. See TPS6291x 3-V to 17-V, 2-A/3-A Low Noise and Low Ripple Buck Converter with Integrated Ferrite Bead Filter Compensation data sheet.

Low ripple and low noise normally indicate two different features of power supply. Ripple refers to the output voltage variation with switching frequency, which is measured by scope and reduced by using second stage LC filter. Noise normally refers to the voltage variation in frequency range of 100Hz-100kHz, which is usually measured with noise spectrum and limited by unique IC design.

For some application which only requires low ripple but not low noise, a second stage LC filter design method is proposed in this application note for general purpose peak current mode buck regulators, which can reduce output voltage ripple amplitude effectively with ensured loop stability. In Part I, the second stage filter components selection method to achieve required output voltage ripple is introduced. In Part II, the stability analysis and design methods are introduced. The proposed method is validated by experiments with internally compensated peak current mode converter TPS62933F. See TPS6293x 3.8-V to 30-V, 2-A, 3-A Synchronous Buck Converters in a SOT583 Package data sheet.