SLVAFQ5 December   2023 TPS51383 , TPS51385 , TPS51386

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Zcap Calculation of Hybrid Capacitors
  6. 3Experimental Verification
  7. 4Loop Stability Analysis With Hybrid Output Capacitor Network
  8. 5Application Design Example of D-CAP3 Converter With a Hybrid Output Capacitors Network
  9. 6Summary
  10. 7References

5 Application Design Example of D-CAP3 Converter With a Hybrid Output Capacitors Network

This section introduces the loop performance for large ESR and small ESR with the same output capacitance value. The TPS51386EVM board is used to perform the loop test and the Bode plot for loop analysis. The setups are Vin= 20 V, Vo= 1.8 V, Iout= 8 A, fsw= 600 kHz, L= 1 µH, and C1= 22 µF (effective value) with 2-mΩ ESR.

Test 1: C2= 150 µF with 5-mΩ ESR.

Equation 5 through Equation 8 are used to calculate the zero and pole, which can be given by ω0= 12.1 kHz, ωz_C1= 3.62 MHz, ωz_C2= 212.3 kHz, and ωp_C2= 1.19 MHz.

Figure 5-1 shows the loop test results, that the crossover frequency is 59.03 kHz, and that the phase margin is 41.98 degrees. The crossover frequency is less than the 1/3×fsw and the loop is stable.

GUID-20231218-SS0I-710Q-N8DT-MPLN85GHCMQQ-low.svg Figure 5-1 Experimental Result With C2= 150 µF, 5-mΩ ESR

Test 2: C2= 150 µF with 70-mΩ ESR.

Equation 5 through Equation 8 are used to calculate the zero and pole, which can be given by ω0= 12.1 kHz, ωz_C1= 3.62 MHz, ωz_C2= 15.2 kHz, ωp_C2= 115.3 kHz.

Figure 5-2 shows the loop test results that the crossover frequency is 202.83 kHz and the phase margin is at 82.18 degrees. The crossover frequency is greater than the 1/3×fsw, which can cause the loop to be unstable.

GUID-20231218-SS0I-3FMW-VMPS-LCVZCPPZVLJC-low.svg Figure 5-2 Experimental Result With C2= 150 µF, 70-mΩ ESR