SLVUBU9A April   2020  – September 2020 TPS63900

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
  3. 2Setup
    1. 2.1 Input/Output Connector and Header Descriptions
      1. 2.1.1  J1, Pin 1 and 2 – VIN
      2. 2.1.2  J1, Pin 3 and 4 – S+/S-
      3. 2.1.3  J1, Pin 5 and 6 – GND
      4. 2.1.4  J2, Pin 1 and 2 – VOUT
      5. 2.1.5  J2, Pin 3 and 4 – S+/S-
      6. 2.1.6  J2, Pin 5 and 6 – GND
      7. 2.1.7  J4 – GND
      8. 2.1.8  JP1 – SEL
      9. 2.1.9  JP2 – ENABLE
      10. 2.1.10 JP3 – CFG1
      11. 2.1.11 JP4 – CFG2
      12. 2.1.12 JP5 – CFG3
      13. 2.1.13 S1, S2, S3, S4, S5, S6 – IC Configuration (R2D Interface)
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic
  6. 5Bill of Materials
  7.   Revision History

S1, S2, S3, S4, S5, S6 – IC Configuration (R2D Interface)

The output voltage is set according to Table 2-1 and Table 2-2. The configuration pins CFG1, CFG2, and CFG3 must not be left floating. Every CFG pin has 16 switches for the different resistor values, but only one switch at a time can be set to ON for each CFG pin. Turn ON the corresponding switches written in Table 2-1 and Table 2-2 VO(2) is set by switch-blocks S1,S2, S4, and S5. VO(1) is set by switch-blocks S3 and S6.

Example: VO(2) (SEL = VO2) is set to 3.4 V and the current limit to unlimited. Set S1.1 to ON for CFG1, S5.1 to ON for CFG2, and S3.1 to ON to keep CFG3 from floating.

Table 2-1 Input Current Limit and Output Voltage VO(2) (SEL = VO2) Settings
OUTPUT VOLTAGE VO(2) (SEL = VO2)INPUT CURRENT LIMIT
UNLIMITED100 mA50 mA25 mA10 mA5 mA2.5 mA1 mA
1.8 VS1.1
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
1.9 VS1.2
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.0 VS1.3
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.1 VS1.4
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.2 VS1.5
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.3 VS1.6
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.4 VS1.7
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.5 VS1.8
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.6 VS4.1
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.7 VS4.2
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.8 VS4.3
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
2.9 VS4.4
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
3.0 VS4.5
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
3.1 VS4.6
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
3.2 VS4.7
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
3.3 VS4.8
S2.1S2.2S2.3S2.4S2.5S2.6S2.7S2.8
3.4 VS1.1
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
3.5 VS1.2
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
3.6 VS1.3
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
3.7 VS1.4
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
3.8 VS1.5
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
3.9 VS1.6
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.0 VS1.7
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.1 VS1.8
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.2 VS4.1
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.3 VS4.2
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.4 VS4.3
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.5 VS4.4
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.6 VS4.5
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.7 VS4.6
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
4.8 VS4.7
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
5.0 VS4.8
S5.1S5.2S5.3S5.4S5.5S5.6S5.7S5.8
Table 2-2 Output Voltage VO(1) (SEL = VO1) Settings
OUTPUT VOLTAGE VO(1) (SEL = VO1)CFG3
1.8 VS3.1
2.0 VS3.2
2.1 VS3.3
2.2 VS3.4
2.3 VS3.5
2.4 VS3.6
2.5 VS3.7
2.6 VS3.8
2.7 VS6.1
2.8 VS6.2
3.0 VS6.3
3.3 VS6.4
3.6 VS6.5
4.0 VS6.6
4.5 VS6.7
5.0 VS6.8