SLVUBY7A October   2020  – October 2022 DRA821U , DRA821U-Q1 , LP8764-Q1 , TPS6594-Q1

 

  1.   User's Guide for Powering DRA821 with TPS6594-Q1 and LP8764-Q1
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE, MCU, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8Additional Resources
  11. 9Revision History

2 Device Versions

There are different versions of the TPS6594-Q1 and LP8764-Q1 devices available with unique NVM settings to support different processor solutions. The unique NVM settings for each PMIC device are optimized per PDN design to support different processors, processing loads, SDRAM types, system functional safety levels, and end product features - such as low power modes, processor interface levels, SD Card, and so forth. The NVM settings can be distinguished using the TI_NVM_ID register. In this user guide, each PMIC device is distinguished by the TI orderable part number, TI_NVM_ID, and TI_NVM_REV values listed in Table 2-1.

Table 2-1 TPS6594-Q1 and LP8764-Q1 NVM Settings and Orderable Part Numbers
PDN USE CASE Orderable Part Number Device Mode TI_NVM_ID TI_NVM_REV
  • Up to 4.25 A(1) on the CORE rail
  • Up to 4.25 A(1) on the CPU rails
  • Up to 3.4 A(1) on the SDRAM, with support for LPDDR4
  • Supports Functional Safety up to ASIL-D level
  • Supports low power modes, including MCU-only, GPIO Retention, and DDR Retention states
  • Supports I/O level of 3.3 V or 1.8 V
  • Supports use of SD card
 TPS6594141B

Primary

 0x1B 0x01
LP876441B1 Secondary 0xB1 0x01
(1) TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC output rail.