SLVUCS8 April   2024 TPS3842 , TPS3842-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 EVM Connectors
      1. 2.1.1 EVM Test Points
      2. 2.1.2 EVM Jumpers
    2. 2.2 EVM Setup and Operation
      1. 2.2.1 Capacitor Sense Time Delay
      2. 2.2.2 Capacitor Reset Time Delay
      3. 2.2.3 Input Power (VDD)
  7. 3Hardware Design Files
    1. 3.1 TPS3842EVM Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5Related Documentation

2.2.3 Input Power (VDD)

The VDD supply is connected through the TP1 and TP10 test points on board. TP1 and TP10 are connected to the VDD pin of the TPS3842 device and TP4, TPS6, TP7, TP8, and TP9 are connected to the GND pin of the device. The supply voltage range is 2.7V to 42V and a 0.1µF decoupling capacitor is recommended at the input for reducing noise that can propagate through the device (included on the EVM board at C2). Table 3-3 details the nominal supply voltage and typical input decoupling capacitor.

Table 2-3 Nominal Supply Parameters
DeviceNominal Supply Voltage (V)Typical Decoupling Capacitor at Input
TPS3842 2.7V to 42V0.1µF