SLYA042 July   2024 FDC1004 , FDC1004-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 CSAs and Input Bias Stage
  6. 3 CSA and Gain Error Factor
  7. 4 Applications for Resistance at Input Pins of Current Sense Amplifiers
    1. 4.1 Input Resistance Design Considerations
  8. 5 Applications for Input Resistance at Reference Pins of Current Sense Amplifiers
    1. 5.1 Bidirectional CSA and Applications
    2. 5.2 Driving CSA Reference Pin With High-Resistance Source Voltage
    3. 5.3 Input Resistance at Reference Pin Design Considerations
  9. 6 Design Procedure and Error Calculation for External Input Resistance on CSA
    1. 6.1 Calculating eEXT for INA185A4 With 110Ω Input Resistors
  10. 7 Design Procedure for Input Resistance on Capacitively-Coupled Current Sense Amplifier
    1. 7.1 Bench Verification of Input eEXT for Capacitively-Coupled Current Sense Amplifiers
  11. 8 Design Procedure for Input Resistance at CSA Reference Pins
  12. 9 Input Resistance Error Test with INA185 Over Temperature
    1. 9.1 Schematic
    2. 9.2 Methods
    3. 9.3 Theoretical Model
    4. 9.4 Data for INA185A4 with 110Ω Input Resistors
      1. 9.4.1 Data Calculations
    5. 9.5 Analysis
  13. 10Input Resistance Error Test with INA191 Over Temperature
    1. 10.1 Schematic
    2. 10.2 Methods
    3. 10.3 Theoretical Model
    4. 10.4 Data for INA191A4 With 2.2kΩ Input Resistors
      1. 10.4.1 Data Analysis
    5. 10.5 Analysis
  14. 11Derivation of VOS, EXT for a Single Stage Current Sense Amplifier (CSA)
  15. 12Summary
  16. 13References

9.2 Methods

The input resistors chosen for the input pins (REXT1 at IN+ and REXT2 at IN-) were 110Ω resistors along with a differential 1nF input capacitor (CDIFF). For the references pins, an approximate 150mV reference voltage was generated with a 49.9kΩ (Ra) and 1.5kΩ (Rb) resistor divider off the VS pin as shown in Table 9-1.

Table 9-1 BOM for INA185A4EVM Modifications
Name (EVM Designator)ValueToleranceDriftPackage
CDIFF (C5D)1nF1%C0G, NP00603
REXT1 (R2D), REXT2 (R4D)110Ω1%50ppm/°C0603
Ra (R5D)49.9kΩ1%50ppm/°C0603
Rb (R6D)1.5kΩ1%50ppm/°C0603

Errors generated from input resistance and reference resistance were distinguished from each other by measuring differential output along with monitoring reference voltage simultaneously.

Input-Output sweeps were run on the EVM at -40°C, 25°C, and 125°C ambient temperatures first with REXT = 0Ω and then with REXT = 110Ω. VOUT was monitored to remain with device's linear output operating region. Linear output region for INA185 is defined at 0.75V < VOUT<4.9V. Additionally, at 125°C, the VCM was swept to measure common-mode rejection (CMR).

Data analysis begins by calculating the total shunt voltage gain using a best-fit line method on all of the VOUT, Differential and the VDIFF values within the designated linear output region. For each VDIFF, an input offset is calculated using linear interpolation with the calculated gain. The final VOS chosen for analysis is the average of all individual offsets pertaining to designated linear output region.

Exact external input resistance errors (EG, EXT, VOS, EXT, EG DRIFT, EXT, VOS Drift, EXT, and CMRREXT) quantified by simply calculating the error difference with and without input resistances.

The loading error to the REF pin (eREF, EXT) is also considered. The measured reference pin (VREF_EFFECTIVE) is compared against a theoretical value using Equation 21 from related Driving Voltage Reference Pins of Current-Sensing Amplifiers, application note. Review this note for more understanding on how these equations were derived.

Errors are compared against a predicted model that uses equations found in Section 6.