SNAA386 November 2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
PCIe began with the first generation, PCIe Gen 1.1, in 2003. The standard is by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). PCIe replaced the original PCI, a parallel communication bus. PCIe uses a serial point-to-point architecture which allows for higher data transfer rates, as devices are not competing for bandwidth on a bus. PCIe also employs differential HCSL or LP-HCSL clocks instead of the PCI LVCMOS clocks, allowing for better noise immunity, and Spread Spectrum Clocking (SSC) for reduction of electromagnetic interference (EMI). This application note discusses the clocking architectures for the PCIe link, as well as the measurement techniques for jitter and waveform integrity.