SNAA386 November   2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Introduction to PCIe
    1. 2.1 The PCIe Link
  6. 3PCIe Clocking Architectures
    1. 3.1 Common Clock Architecture
    2. 3.2 Separate Reference Architecture
    3. 3.3 Spread Spectrum Clocking
    4. 3.4 PCIe REFCLK Topology
    5. 3.5 Noise Folding
  7. 4PCIe Clocking Specifications
    1. 4.1 REFCLK Output Format
    2. 4.2 PCIe Jitter Requirements
    3. 4.3 PCIe Time Domain Requirements
  8. 5REFCLK Measurement Technique
    1. 5.1 Clock Generator Measurement Results
      1. 5.1.1 PNA Measurement Result without SSC
      2. 5.1.2 PCIe Filtered PNA Result without SSC
      3. 5.1.3 PNA Measurement Result, With SSC
      4. 5.1.4 PCIe Filtered PNA Result, With SSC
      5. 5.1.5 Time Domain PCIe Measurement Result
    2. 5.2 Clock Buffer Measurement Results
      1. 5.2.1 PNA Measurement Result
      2. 5.2.2 PCIe Filtered PNA Result
      3. 5.2.3 Time Domain PCIe Measurement Result
  9. 6Texas Instruments Products with PCIe Compliance
  10. 7Summary
  11. 8References

2.1 The PCIe Link

In a PCIe link, signals are transferred over connection pairs referred to as lanes. One lane for transmitting data (TX), and another lane for receiving data (RX). PCIe is a scalable architecture. Each link can be comprised of up to 32 lanes at once for maximizing data throughput. Most systems typically employ only 16 lanes. Figure 2-1 shows an example of a standard PCIe link.

GUID-20231120-SS0I-DHSL-ZQZS-TTXLCKPT9LJK-low.svg Figure 2-1 PCIe Link

As the PCIe standard has evolved, the raw bit rate per lane has improved. Modern-day PCIe Generation 6.0 allows for a bit rate of 64 Gb/s. Table 2-1 shows the data rate for each PCIe generation.

Table 2-1 PCIe Standard Bit Rate by Generation
PCIe Generation Debut Year Raw Bit Rate
PCIe 1.1 2005 2.5 Gb/s
PCIe 2.1 2009 5.0 Gb/s
PCIe 3.1 2013 8.0 Gb/s
PCIe 4.0 2017 16.0 Gb/s
PCIe 5.0 2019 32.0 Gb/s
PCIe 6.0 2021 64.0 Gb/s

With 8 bits per byte, the data throughput per lane per direction for PCIe 6.0 is up to 8 GB/s per direction per lane. In a 16-lane system, throughput up to 256 GB/s is achievable.