SNAA386 November   2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Introduction to PCIe
    1. 2.1 The PCIe Link
  6. 3PCIe Clocking Architectures
    1. 3.1 Common Clock Architecture
    2. 3.2 Separate Reference Architecture
    3. 3.3 Spread Spectrum Clocking
    4. 3.4 PCIe REFCLK Topology
    5. 3.5 Noise Folding
  7. 4PCIe Clocking Specifications
    1. 4.1 REFCLK Output Format
    2. 4.2 PCIe Jitter Requirements
    3. 4.3 PCIe Time Domain Requirements
  8. 5REFCLK Measurement Technique
    1. 5.1 Clock Generator Measurement Results
      1. 5.1.1 PNA Measurement Result without SSC
      2. 5.1.2 PCIe Filtered PNA Result without SSC
      3. 5.1.3 PNA Measurement Result, With SSC
      4. 5.1.4 PCIe Filtered PNA Result, With SSC
      5. 5.1.5 Time Domain PCIe Measurement Result
    2. 5.2 Clock Buffer Measurement Results
      1. 5.2.1 PNA Measurement Result
      2. 5.2.2 PCIe Filtered PNA Result
      3. 5.2.3 Time Domain PCIe Measurement Result
  9. 6Texas Instruments Products with PCIe Compliance
  10. 7Summary
  11. 8References

5.1.2 PCIe Filtered PNA Result without SSC

Table 5-2 shows the result of the PNA capture after post processing using the PCIe Gen 6.0 filters. Each possible combination of PLL and CDR parameters is tested, resulting in 16 total filter combinations, all of which pass the PCIe Gen 6.0 limit of 100 fs of RMS jitter. The maximum noise fold is used in this case, with the noise floor extended to 200 MHz offset from the carrier.

Table 5-2 LMK3H0102 Detailed PCIe Gen 6 Measurements, Non-SSC
PCIe Gen Clock Architecture Noise Fold Filter Combination PLL1 f1 PLL1 ζ1 PLL2 f2 PLL2 ζ2 CDR f3 Jitter (fs) Limit (fs) Status
6 CC 3 1 5.000e+5 14.0 5.000e+5 14.0 1.000e+7 4.864 100.0 PASS
6 CC 3 2 5.000e+5 14.0 5.000e+5 0.73 1.000e+7 4.209 100.0 PASS
6 CC 3 3 5.000e+5 14.0 1.000e+6 14.0 1.000e+7 8.117 100.0 PASS
6 CC 3 4 5.000e+5 14.0 1.000e+6 0.73 1.000e+7 5.873 100.0 PASS
6 CC 3 5 5.000e+5 0.73 5.000e+5 14.0 1.000e+7 4.209 100.0 PASS
6 CC 3 6 5.000e+5 0.73 5.000e+5 0.73 1.000e+7 3.281 100.0 PASS
6 CC 3 7 5.000e+5 0.73 1.000e+6 14.0 1.000e+7 8.180 100.0 PASS
6 CC 3 8 5.000e+5 0.73 1.000e+6 0.73 1.000e+7 5.654 100.0 PASS
6 CC 3 9 1.000e+6 14.0 5.000e+5 14.0 1.000e+7 8.117 100.0 PASS
6 CC 3 10 1.000e+6 14.0 5.000e+5 0.73 1.000e+7 8.180 100.0 PASS
6 CC 3 11 1.000e+6 14.0 1.000e+6 14.0 1.000e+7 9.352 100.0 PASS
6 CC 3 12 1.000e+6 14.0 1.000e+6 0.73 1.000e+7 8.525 100.0 PASS
6 CC 3 13 1.000e+6 0.73 5.000e+5 14.0 1.000e+7 5.873 100.0 PASS
6 CC 3 14 1.000e+6 0.73 5.000e+5 0.73 1.000e+7 5.654 100.0 PASS
6 CC 3 15 1.000e+6 0.73 1.000e+6 14.0 1.000e+7 8.525 100.0 PASS
6 CC 3 16 1.000e+6 0.73 1.000e+6 0.73 1.000e+7 6.563 100.0 PASS