SNAA386 November   2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Introduction to PCIe
    1. 2.1 The PCIe Link
  6. 3PCIe Clocking Architectures
    1. 3.1 Common Clock Architecture
    2. 3.2 Separate Reference Architecture
    3. 3.3 Spread Spectrum Clocking
    4. 3.4 PCIe REFCLK Topology
    5. 3.5 Noise Folding
  7. 4PCIe Clocking Specifications
    1. 4.1 REFCLK Output Format
    2. 4.2 PCIe Jitter Requirements
    3. 4.3 PCIe Time Domain Requirements
  8. 5REFCLK Measurement Technique
    1. 5.1 Clock Generator Measurement Results
      1. 5.1.1 PNA Measurement Result without SSC
      2. 5.1.2 PCIe Filtered PNA Result without SSC
      3. 5.1.3 PNA Measurement Result, With SSC
      4. 5.1.4 PCIe Filtered PNA Result, With SSC
      5. 5.1.5 Time Domain PCIe Measurement Result
    2. 5.2 Clock Buffer Measurement Results
      1. 5.2.1 PNA Measurement Result
      2. 5.2.2 PCIe Filtered PNA Result
      3. 5.2.3 Time Domain PCIe Measurement Result
  9. 6Texas Instruments Products with PCIe Compliance
  10. 7Summary
  11. 8References

4.2 PCIe Jitter Requirements

For Common Clock architectures, the PCIe standard sets an upper bound on the RMS jitter allowed through the filters, defined by Equation 5. This limit applies for each filter combination in a given generation. If the jitter after one set of filters exceeds the limits, then the REFCLK does not meet the requirements for that PCIe generation. Table 4-1 shows the jitter limits for Common Clock architectures after the filtering is applied. Note that these limits apply for both CC and CCS. For Separate Reference architectures, a phase jitter limit is not set by the PCIe standard; instead, the limits are left up to the engineer designing the system.

Table 4-1 PCIe REFCLK Phase Jitter Limit by Generation
PCIe Generation REFCLK Phase Jitter Limit (ps RMS)
PCIe 1.1 86
PCIe 2.1 3.1
PCIe 3.1 1.0
PCIe 4.0 0.5
PCIe 5.0 0.15
PCIe 6.0 0.1