SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD14 – 24-bit Capture Channel Control Register 0
Address FFF7FD18 – 24-bit Capture Channel Control Register 1 – only on ‘A64 and 128
The ‘a64 and ‘128 devices have T24CAPCTRL0 and 1. Other devices have T24CAPCTRL.
5 | 4 | 3 | 2 | 1 | 0 |
CAP_SEL | EDGE | CAP_INT_ENA | CAP_INT_FLAG |
R/W-00 | R/W-00 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
5-4 | CAP_SEL | R/W | 00 | Capture Pin Select 00 = TCAP pin (Default) 01 = SCI_RX[0] pin 10 = SCI_RX[1] pin 11 = SYNC pin |
3-2 | EDGE | R/W | 00 | Input Capture Edge Select 00 = No Capture (Default) 01 = Rising Edge 10 = Falling Edge 11 = Both Edges |
1 | CAP_INT_ENA | R/W | 0 | Input Capture Interrupt Enable 0 = Disables 24-bit input capture interrupt (Default) 1 = Enables 24-bit input capture interrupt |
0 | CAP_INT_FLAG | R/W | 0 | Flag which indicates a valid input capture event. This bit is cleared by writing a ‘1’ to it or by reading the corresponding Capture Channel Data Register. If a clear and a valid capture event occur at the same time, the flag will remain high (set has priority versus clear). 0 = No valid capture event since last clear 1 = Valid capture event since last clear |