SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7FD2C
1 | 0 |
CMP_INT_ENA | CMP_INT_FLAG |
R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
1 | CMP_INT_ENA | R/W | 0 | Output Compare Channel Interrupt 0 = Disables Output Compare Channel Interrupt (Default) 1 = Enables Output Compare Channel Interrupt |
0 | CMP_INT_FLAG | R/W | 0 | Indicates a valid output compare event. Bit can be cleared by writing a ‘1’ to the bit or by rewriting the 24-bit Output Compare Channel Data Register. If a clear and compare event occur at the same time, the flag will remain high (set has priority versus clear). 0 = No compare event since last clear 1 = Compare event since last clear |