SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFFE0
The system exception control Register contains bits that allow the user to generate a software reset. The OVR bits disable some reset/abort conditions when TRST is high.
15 | 14 | 13 | 8 |
RESET | Reserved |
R/W-01 | R-0 |
7 | 3 | 2 | 1 | 0 |
Reserved | PACCOVR | ACCOVR | ILLOVR |
R-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESET | R/W | 01 | Software Reset Enable. These bits always read as 01 01 = No reset 1X = Global system reset (X = don’t care) X0 = Global system reset (X = don’t care) |
13-3 | Reserved | R | 0 | |
2 | PACCOVR | R/W | 0 | Peripheral Access Violation Override 0 = Peripheral access violation error causes a reset or abort (Default) 1 = No action taken on a peripheral access violation |
1 | ACCOVR | R/W | 0 | Memory Access Reset Override 0 = Memory access violation error causes a reset or abort (Default) 1 = No action taken on an illegal address |
0 | ILLOVR | R/W | 0 | Illegal Address Reset Override 0 = Illegal address causes a reset or abort (Default) 1 = No action taken on an illegal address |