SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address 0003001C
31 | 28 | 27 | 24 |
START_VALUE_SEL | STEP_SIZE |
R/W-0000 | R/W-00 0000 0000 0000 0000 |
23 | 16 |
STEP_SIZE |
R/W-00 0000 0000 0000 0000 |
15 | 10 | 9 | 8 |
STEP_SIZE | CLKS_PER_STEP |
R/W-00 0000 0000 0000 0000 | R/W-0 0000 |
7 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKS_PER_STEP | DPWM3_TRIG_EN | DPWM2_TRIG_EN | DPWM1_TRIG_EN | DPWM0_TRIG_EN | RAMP_EN |
R/W-0 0000 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | START_VALUE _SEL | R/W | 0000 | Configures comparator ramp starting value 0 = Filter 0 Output (Bits 17-11) (Default) 1 = Filter 1 Output (Bits 17-11) 2 = Filter 2 Output (Bits 17-11) 3 = Analog Comparator Threshold A Value 4 = Analog Comparator Threshold B Value 5 = Analog Comparator Threshold C Value 6 = Analog Comparator Threshold D Value 7 = Analog Comparator Threshold E Value 8 = Analog Comparator Threshold F Value 9 = Analog Comparator Threshold G Value |
27-10 | STEP_SIZE | R/W | 00 0000 0000 0000 0000 | Programmable 18-bit unsigned comparator step with Bits 27:24 representing the integer portion of the comparator step (0-15 Comparator steps of 19.5mV each) and Bits 23:10 representing the fractional portion of the comparator step |
9-5 | CLKS_PER_STEP | R/W | 0 0000 | Selects number of MCLK (HFO_OSC/8) clock cycles per comparator step where number of subcycles can vary from 1 to 32 0 = 1 MCLK clock cycles per step (Default) 1 = 2 MCLK clock cycles per step 2 = 3 MCLK clock cycles per step ……. 31 = 32 MCLK clock cycles per step |
4 | DPWM3_TRIG _EN | R/W | 0 | Enables DPWM Trigger from DPWM 3 to Analog Comparator Ramp 0 0 = DPWM 3 trigger not routed to Analog Comparator Ramp 0 (Default) 1 = DPWM 3 trigger routed to Analog Comparator Ramp 0 |
3 | DPWM2_TRIG _EN | R/W | 0 | Enables DPWM Trigger from DPWM 2 to Analog Comparator Ramp 0 0 = DPWM 2 trigger not routed to Analog Comparator Ramp 0 (Default) 1 = DPWM 2 trigger routed to Analog Comparator Ramp 0 |
2 | DPWM1_TRIG _EN | R/W | 0 | Enables DPWM Trigger from DPWM 1 to Analog Comparator Ramp 0 0 = DPWM 1 trigger not routed to Analog Comparator Ramp 0 (Default) 1 = DPWM 1 trigger routed to Analog Comparator Ramp 0 |
1 | DPWM0_TRIG _EN | R/W | 0 | Enables DPWM Trigger from DPWM 0 to Analog Comparator Ramp 0 0 = DPWM 0 trigger not routed to Analog Comparator Ramp 0 (Default) 1 = DPWM 0 trigger routed to Analog Comparator Ramp 0 |
0 | RAMP_EN | R/W | 0 | Enable for Analog Comparator Ramp 0 0 = Analog Comparator Ramp disabled (Default) 1 = Analog Comparator Ramp enabled |