SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFFFFD00
13 | 12 | 11 | 9 | 8 | 7 | 4 | 3 | 2 | 1 | 0 |
LEAD | TRAIL | Rsvd | ACTIVE | ENDIAN | Rsvd | WIDTH |
R/W-00 | R/W-000 | R-0 | R/W-0000 | R-0 | R-0 | R/W-00 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
13-12 | LEAD | R/W | 00 | Address setup time cycles (write operations) 00 = No setup time required (Default) 01 = Write strobe is delayed one cycle 10 = Write strobe is delayed two cycles 11 = Write strobe is delayed three cycles |
11-9 | TRAIL | R/W | 000 | Number of Trailing wait states. Determine the trailing wait states after read and write operations to the memory associated with the chip select corresponding to the wait states. |
8 | Reserved | R | 0 | |
7-4 | ACTIVE | R/W | 0000 | Active Wait states (both read/write operations) 0000 = 0 Wait states (Default) 0001 = 1 Wait states 0010 = 2 Wait states 0011 = 3 Wait states 0100 = 4 Wait states 0101 = 5 Wait states 0110 = 6 Wait states 0111 = 7 Wait states 1000 = 8 Wait states 1001 = 9 Wait states 1010 = 10 Wait states 1011 = 11 Wait states 1100 = 12 Wait states 1101 = 13 Wait states 1110 = 14 Wait states 1111 = 15 Wait states |
3 | ENDIAN | R | 0 | Endian Mode Identification 0 = CPU configured in big endian mode 1 = CPU configured in little endian mode |
2 | Reserved | R | 0 | |
1-0 | WIDTH | R/W | 00 | Data Width for Memories 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = Reserved |