SNIU028D February 2016 – September 2020 UCD3138 , UCD3138064 , UCD3138064A , UCD3138128 , UCD3138A , UCD3138A64
Address FFF7F038
23 | 16 | 15 | 8 | 7 | 4 | 3 | 0 |
DPWM_DUTY | DPWM_PERIOD | Reserved | TEST_MODE |
R/W-0000 0000 | R/W-0000 0000 | R-0000 | R/W-0000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23-16 | DPWM_DUTY | R/W | 0000 0000 | Configures Pulse Width/Duty Cycle for DPWM output to Current Sharing circuit. Resolution of LSB equals period of MCLK clock (32 ns). |
15-8 | DPWM_PERIOD | R/W | 0000 0000 | Configures Period for DPWM output to Current Sharing circuit. Output period equals DPWM_PERIOD+1 * LSB resolution. Resolution of LSB equals period of MCLK clock |
7-4 | Reserved | R/W | 0000 | |
3-0 | TEST_MODE | R/W | 0000 | Controls Current Sharing Operation |
Current Sharing Mode | CSCTRL.bit.TEST_MODE | Switch θ1 | Switch θ2 | Digital-PWM |
---|---|---|---|---|
Tri-state or Slave mode | 0 | OFF | OFF | OFF |
PWM average current Bus | 1 | ON | OFF | ACTIVE |
Analog average current Bus or Master mode | 3 | OFF | ON | OFF |